公开(公告)号：US09530863B1

公开(公告)日：2016-12-27

申请号：US15097574

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl Radens ,  Steven J. Bentley ,  Brian A. Cohen ,  Kwan-Yong Lim

IPC: H01L21/306 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming a layer of a bottom spacer material around the vertically oriented channel semiconductor structure and forming a sacrificial material layer above the layer of a bottom spacer material. In this example, the method further includes forming a sidewall spacer adjacent the vertically oriented channel semiconductor structure and above an upper surface of the sacrificial material layer, removing the sacrificial material layer so as to define a replacement gate cavity between a bottom surface of the sidewall spacer and the layer of a bottom spacer material, and forming a replacement gate structure in the replacement gate cavity.

Abstract translation: 本文中公开的一种说明性方法包括形成垂直取向的沟道半导体结构，在垂直取向的沟道半导体结构周围形成底部间隔物材料的层，并在底部间隔物材料的层的上方形成牺牲材料层。 在该示例中，该方法还包括形成邻近垂直取向的沟道半导体结构并且在牺牲材料层的上表面上方的侧壁间隔物，去除牺牲材料层，以便在侧壁的底表面之间限定替换栅腔 间隔物和底部间隔物材料的层，并且在替换浇口腔中形成替代浇口结构。

公开(公告)号：US09530866B1

公开(公告)日：2016-12-27

申请号：US15097621

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl Radens ,  Steven J. Bentley ,  Brian A. Cohen ,  Kwan-Yong Lim

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L29/66666 ,  B82Y10/00 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/7827

Abstract: Forming a first sidewall spacer adjacent a vertically oriented channel semiconductor structure (“VCS structure’) and adjacent a cap layer, performing at least one planarization process so as to planarize an insulating material and expose an upper surface of the cap layer and an upper surface of the first spacer and removing a portion of the first spacer and an entirety of the cap layer so as to thereby expose an upper surface of the VCS structure and define a spacer/contact cavity above the VCS structure and the first spacer. The method also includes forming a second spacer in the spacer/contact cavity, forming a top source/drain region in the VCS structure and forming a top source/drain contact within the spacer/contact cavity that is conductively coupled to the top source/drain region, wherein the conductive contact physically contacts the second spacer in the spacer/contact cavity.

Abstract translation: 形成与垂直取向的沟道半导体结构（“VCS结构”）相邻并且与覆盖层相邻的第一侧壁间隔物，执行至少一个平坦化处理，以平坦化绝缘材料并暴露盖层的上表面和上表面 并且去除所述第一间隔物的一部分和所述盖层的整体，从而暴露所述VCS结构的上表面并且在所述VCS结构和所述第一间隔物之上限定间隔物/接触腔。 该方法还包括在间隔物/接触腔中形成第二间隔物，在VCS结构中形成顶部源极/漏极区域，并在间隔物/接触腔内形成顶部源极/漏极接触，导电耦合到顶部源极/漏极 区域，其中所述导电接触物质地接触所述间隔件/接触腔中的所述第二间隔件。

公开(公告)号：US09418903B2

公开(公告)日：2016-08-16

申请号：US14283633

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl Radens

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/308 ,  H01L21/3083 ,  H01L27/1211 ,  H01L29/66818

Abstract: Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as SRAM design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (Vt) for a part of the fin, rendering that part of the fin electrically inactive, which changes the effective device width (Weff). Other fins are unclad, and provide maximum area of constant threshold voltage. In this way, the effective device width of some devices is reduced. Therefore, the effective device width is controllable by controlling the level of cladding of the fin.

Abstract translation: 本发明的实施例提供了通过引入分数有效装置宽度可以放宽有效宽度的固有离散化的方法和结构，从而为诸如SRAM设计优化的设计应用提供了更大的灵活性。 一些翅片的一部分用覆盖层或功函材料包覆以改变鳍的一部分的阈值电压（Vt），使得该部分鳍电活动，这改变了有效器件宽度（Weff）。 其他翅片不包括，并提供最大面积的恒定阈值电压。 以这种方式，某些设备的有效设备宽度就会降低。 因此，通过控制翅片的包层水平来控制有效的装置宽度。

公开(公告)号：US09472558B1

公开(公告)日：2016-10-18

申请号：US14940499

申请日：2015-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Carl Radens ,  Robert C. Wong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L27/11 ,  H01L23/528 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1116 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0688 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Disclosed are semiconductor structures and methods of forming them. The structures include field effect transistors (FETs) with different type conductivities in different levels, respectively, of the same fin, wherein the numbers of FETs in the different levels are different. Specifically, in a fin, a first semiconductor layer has source/drain and channel regions for a first and a second transistor and a second semiconductor layer has source/drain and channel regions for a third transistor with a different type conductivity than first and second transistors. A gate is on the top surface and sides of the first semiconductor layer at the channel region of the first transistor. Another gate has a lower portion on the sides of the first semiconductor layer at the channel region of the second transistor and an upper portion on the top surface and sides of the second semiconductor layer at the channel region of the third transistor.

Abstract translation: 公开了半导体结构及其形成方法。 该结构分别包括具有不同级别的不同类型电导率的场效应晶体管（FET），其中不同级别的FET的数量是不同的。 具体地，在散热片中，第一半导体层具有用于第一和第二晶体管的源极/漏极和沟道区，并且第二半导体层具有用于具有与第一和第二晶体管不同的导电类型的第三晶体管的源极/漏极和沟道区 。 栅极位于第一晶体管的沟道区的第一半导体层的顶表面和侧面上。 另一个栅极在第二晶体管的沟道区域处具有在第一半导体层的侧面上的下部，在第三晶体管的沟道区域处的第二半导体层的顶部表面和侧面上的上部。