公开(公告)号：US08835328B2

公开(公告)日：2014-09-16

申请号：US13763399

申请日：2013-02-08

Applicant: Globalfoundries, Inc.

Inventor： Wontae Hwang ,  Il Goo Kim ,  Dae-Han Choi ,  Sang Cheol Han

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L29/66795 ,  Y10S438/946 ,  Y10S438/947

Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.

Abstract translation: 本文提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供覆盖在半导体衬底上的心轴层，并将心轴层图案化成心轴结构。 该方法还包括在心轴结构之间形成保护层。 间隔件形成在每个心轴结构周围并且覆盖保护层以限定保护层的暴露区域和保护层的覆盖区域。 使用间隔件和心轴结构作为掩模来蚀刻保护层的暴露区域。 从保护层的覆盖区域移除间隔物。 保护层的覆盖区域形成用于蚀刻半导体衬底的掩模段。 该方法去除芯棒结构并蚀刻暴露在掩模段之间的半导体衬底以形成半导体鳍结构。

公开(公告)号：US08993445B2

公开(公告)日：2015-03-31

申请号：US13740343

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dae-Han Choi ,  Dae Geun Yang ,  Chang Ho Maeng ,  Wontae Hwang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  B44C1/22 ,  C25F3/00 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

Abstract translation: 提供了通过选择性地蚀刻栅极结构侧壁以促进随后的侧壁间隔隔离来促进制造半导体器件的方法。 该方法包括例如：在栅极结构上提供具有保护层的栅极结构，栅极结构包括一个或多个侧壁; 沿着至少一个侧壁选择性地去除所述栅极结构的一部分以部分地切割所述保护层; 以及在所述栅极结构的侧壁上形成侧壁间隔物，所述侧壁间隔物的一部分至少部分地填充所述保护层的部分底切，并且位于所述保护层的下方， 。 在某些实施例中，选择性去除包括用掺杂剂注入侧壁以产生栅极结构的掺杂区域，并且随后至少部分地去除栅极结构的掺杂区域， 栅极结构的未掺杂区域。

公开(公告)号：US20160005868A1

公开(公告)日：2016-01-07

申请号：US14320932

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Jing Wan ,  Dae-Han Choi

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Embodiments of the present invention provide a fin-type field effect transistor (finFET) with confined epitaxy. A protective layer is formed on a fin. The protective layer is recessed to expose the fin top. A fin cavity is formed in the fin. An epitaxial region is formed in the fin cavity. The epitaxial region has a confined portion and a diamond-shaped portion, resulting in increased epitaxial volume. The increased epitaxial volume can result in enhanced carrier mobility and improved device performance.

Abstract translation: 本发明的实施例提供了具有有限外延的翅片型场效应晶体管（finFET）。 在翅片上形成保护层。 保护层凹入以暴露翅片顶部。 翅片中形成翅片腔。 在翅片腔中形成外延区域。 外延区具有限制部分和菱形部分，导致增加的外延体积。 增加的外延体积可以导致增强的载流子迁移率和改进的器件性能。

公开(公告)号：US09105478B2

公开(公告)日：2015-08-11

申请号：US14064840

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Wei ,  Mariappan Hariharaputhiran ,  Dae Geun Yang ,  Dae-Han Choi ,  Xiang Hu ,  Richard J. Carter ,  Akshey Sehgal

IPC: H01L21/302 ,  H01L21/033 ,  G03F1/50

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

公开(公告)号：US09034767B1

公开(公告)日：2015-05-19

申请号：US14076386

申请日：2013-11-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Dae-Han Choi ,  Dae Geun Yang ,  Taejoon Han ,  Andy Wei

IPC: H01L21/311 ,  H01L21/30 ,  H01L21/308

CPC classification number: H01L21/0337

Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

Abstract translation: 通过以下方式促进掩模图案形成：提供掩模结构，其包括设置在基板结构上方的至少一个牺牲间隔结构; 将掩模层保形地设置在掩模结构上; 选择性地去除间隔层，至少部分地留下沿着至少一个牺牲间隔结构的侧壁的侧壁间隔物，并且在衬底结构上方提供至少一个额外的牺牲间隔物，该至少一个额外的牺牲隔离物 间隔件与所述至少一个牺牲间隔结构设置成间隔开的关系; 以及去除所述至少一个牺牲间隔结构，将所述侧壁间隔物和所述至少一个另外的牺牲隔离物留在所述衬底结构上作为掩模图案的一部分。

公开(公告)号：US08969205B2

公开(公告)日：2015-03-03

申请号：US13852496

申请日：2013-03-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： HongLiang Shen ,  Dae-Han Choi ,  Dae Geun Yang ,  Jung Yu Hsieh

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/3086 ,  H01L21/28114 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below.

Abstract translation: 制造中的中间半导体结构包括硅半导体衬底，在衬底上的氮化硅（SiN）的硬掩模和在硬掩模上的多晶硅或非晶硅的牺牲层。 牺牲层被图案化成侧壁间隔物，用于与侧壁间隔物例如可流动氧化物的组成基本上不同的填充材料的心轴。 去除心轴使得侧壁间隔件具有提供粗糙三角形形状的垂直锥形内侧壁和外侧壁。 粗糙的三角形侧壁间隔物用作硬掩模以在下面对SiN硬掩模进行图案化。