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    METHOD OF SIMULTANEOUS LITHOGRAPHY AND ETCH CORRECTION FLOW
    3.
    发明申请
    METHOD OF SIMULTANEOUS LITHOGRAPHY AND ETCH CORRECTION FLOW 有权
    同时计算和蚀刻校正流程的方法

    公开(公告)号：US20170004233A1

    公开(公告)日：2017-01-05

    申请号：US14788296

    申请日：2015-06-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Geng Han ,  Scott M. Mansfield ,  Dominique Nguyen-Ngoc ,  Donald J. Samuels ,  Ramya Viswanathan

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G03F1/36 ,  G03F1/144 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/0274

    Abstract: A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.

    Abstract translation: 一种掩模校正方法，其中两个独立的过程模型被同时分析和共同优化。 在该方法中，在计算机系统上运行第一光刻过程模型模拟，其导致在第一处理窗口中产生第一掩模尺寸。 同时，运行第二硬掩模开放蚀刻工艺模型模拟，导致在第二处理窗口中产生第二掩模尺寸。 在单个迭代循环中分析每个第一光刻处理模型和第二硬掩模开放蚀刻工艺模拟模拟，并且获得在光刻和蚀刻之间优化的公共工艺窗口（PW），使得所述第一掩模尺寸和第二掩模尺寸在所述 普通PW。 此外，产生蚀刻模型形式，其考虑由于三维光致抗蚀剂轮廓的变化而导致的蚀刻图案的差异，该模型形式包括与光学图像直接相关的光学和密度项。

    HYBRID OPTICAL AND EUV LITHOGRAPHY
    4.
    发明申请
    HYBRID OPTICAL AND EUV LITHOGRAPHY 审中-公开

    公开(公告)号：US20200159105A1

    公开(公告)日：2020-05-21

    申请号：US16191589

    申请日：2018-11-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jia Zeng ,  Guillaume Bouche ,  Lei Sun ,  Geng Han

    IPC: G03F1/24 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/311

    Abstract: Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.

    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
    5.
    发明申请
    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS 审中-公开

    公开(公告)号：US20190006232A1

    公开(公告)日：2019-01-03

    申请号：US16103372

    申请日：2018-08-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

    IPC: H01L21/768 ,  H01L29/40 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02

    Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

    Method of simultaneous lithography and etch correction flow
    7.
    发明授权
    Method of simultaneous lithography and etch correction flow 有权

    公开(公告)号：US09910348B2

    公开(公告)日：2018-03-06

    申请号：US14788296

    申请日：2015-06-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Geng Han ,  Scott M. Mansfield ,  Dominique Nguyen-Ngoc ,  Donald J. Samuels ,  Ramya Viswanathan

    IPC: G06F17/50 ,  G03F1/00 ,  G03F1/36 ,  H01L21/027

    CPC classification number: G03F1/36 ,  G03F1/144 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/0274

    Abstract: A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.

    Predicting process fail limits
    8.
    发明授权
    Predicting process fail limits 有权
    预测过程失败限制

    公开(公告)号：US09471743B1

    公开(公告)日：2016-10-18

    申请号：US14674571

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Geng Han ,  Scott M. Mansfield ,  Ramya Viswanathan

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/12 ,  Y02P90/265

    Abstract: In an approach for predicting a process fail limit for a semiconductor manufacturing process, a computer determines a potential working process condition for each of a plurality of process parameters varied in forming a test wafer feature. The computer determines a process sigma value for each of the plurality of process parameters in forming the test wafer feature and a measurement sigma value. The computer evaluates a set of measurements of the test wafer feature compared to an acceptable wafer feature dimension, where each measurement of the set of measurements is a pass or fail as compared to the acceptable wafer feature dimension. The computer determines whether one or more fails are evaluated compared to the acceptable wafer feature dimension. The computer produces a predicted process fail limit based, at least in part, on the evaluation of fails, the measurement sigma value, and a desired target sigma value.

    Abstract translation: 在用于预测半导体制造工艺的工艺故障限制的方法中，计算机确定在形成测试晶片特征时变化的多个工艺参数中的每一个的潜在工作工艺条件。 在形成测试晶片特征和测量西格玛值时，计算机确定多个工艺参数中的每个工艺参数的工艺sigma值。 与可接受的晶片特征尺寸相比，计算机评估测试晶片特征的一组测量，其中与可接受的晶片特征尺寸相比，该组测量的每个测量是通过或失败。 与可接受的晶片特征尺寸相比，计算机确定是否评估一个或多个故障。 该计算机至少部分地基于失败的评估，测量西格玛值和期望的目标σ值产生预测的过程失败限制。

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