公开(公告)号：US09865681B1

公开(公告)日：2018-01-09

申请号：US15453170

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  John Zhang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28088 ,  H01L21/30604 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66568

Abstract: Multi-threshold voltage (Vt) nanowire devices are fabricated using a self-aligned methodology where gate cavities having a predetermined geometry are formed proximate to channel regions of respective devices. The gate cavities are then backfilled with a gate conductor. By locally defining the cavity geometry, the thickness of the gate conductor is constrained and hence the threshold voltage for each device can be defined using a single deposition process for the gate conductor layer. The self-aligned nature of the method obviates the need to control gate conductor layer thicknesses using deposition and/or etch processes.

公开(公告)号：US09773708B1

公开(公告)日：2017-09-26

申请号：US15245634

申请日：2016-08-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John Zhang ,  Steven Bentley ,  Kwan-Yong Lim

IPC: H01L21/8238 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Devices and methods of fabricating vertical field effect transistors on semiconductor devices are provided. One intermediate semiconductor includes: a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin; a high-k layer and a work function metal over the bottom spacer layer and around the plurality of fins; a top spacer above the high-k layer and the work function metal and surrounding a top area of the fins; a top source/drain structure over each fin; a dielectric capping layer over the top source/drain structure; a fill metal surrounding the work function metal; and a liner.

公开(公告)号：US20190355615A1

公开(公告)日：2019-11-21

申请号：US16525601

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

公开(公告)号：US20190056671A1

公开(公告)日：2019-02-21

申请号：US15681007

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  John Zhang ,  Shao Beng Law ,  Guoxiang Ning ,  Xunyuan Zhang ,  Ruilong Xie

IPC: G03F7/20 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  C23C14/22 ,  C23C16/455

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.

公开(公告)号：US20180248046A1

公开(公告)日：2018-08-30

申请号：US15445392

申请日：2017-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Jiehui Shu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78684

Abstract: A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

公开(公告)号：US09916982B1

公开(公告)日：2018-03-13

申请号：US15383461

申请日：2016-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Haigou Huang ,  John Zhang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/283

CPC classification number: H01L21/823437 ,  H01L21/283 ,  H01L21/8234 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78

Abstract: Structures for use in a replacement gate process involving a field-effect transistor and methods for forming such structures. A first dielectric layer is formed adjacent to a dummy gate structure, and a second dielectric layer is formed on the first dielectric layer. After the second dielectric layer is formed, a portion of the dummy gate structure is removed with an etching process to cut the dummy gate structure into disconnected segments. The second dielectric layer caps the first dielectric layer when the portion of the dummy gate structure is removed. The second dielectric layer has a higher etch rate selectivity than the first dielectric layer to the etching process.

公开(公告)号：US20190341475A1

公开(公告)日：2019-11-07

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US10388729B2

公开(公告)日：2019-08-20

申请号：US15155761

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John Zhang ,  Lawrence Clevenger ,  Kangguo Cheng ,  Balasubramanian Haran

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/165

Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.

公开(公告)号：US10586860B2

公开(公告)日：2020-03-10

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/3065

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US10418272B1

公开(公告)日：2019-09-17

申请号：US15976326

申请日：2018-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.