公开(公告)号：US10079248B2

公开(公告)日：2018-09-18

申请号：US15355231

申请日：2016-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Mark D. Jaffe ,  John J. Pekarik

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/265 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76838 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78654

Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.

公开(公告)号：US20170365775A1

公开(公告)日：2017-12-21

申请号：US15690828

申请日：2017-08-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H01L41/293 ,  H01L41/25 ,  G06F17/50 ,  H01L21/768 ,  H01L23/00 ,  H01L41/08 ,  H03H9/64 ,  H01L23/48 ,  H01L27/06 ,  H01L25/16 ,  H01L23/66 ,  H01L49/02

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

公开(公告)号：US20170186643A1

公开(公告)日：2017-06-29

申请号：US14982576

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US10164101B1

公开(公告)日：2018-12-25

申请号：US15790707

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. Camillo-Castillo ,  Anthony K. Stamper ,  Vibhor Jain ,  Mark D. Jaffe

IPC: H01L21/82 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/764 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with improved channel mobility and methods of manufacture. A structure includes: a curved beam structure formed from at least one stressed material; a cavity below the curved beam structure; and at least one semiconductor device on a top portion or a bottom portion of the curved beam structure whose carrier mobility is increased or decreased by a curvature of the curved beam structure.

公开(公告)号：US20170330832A1

公开(公告)日：2017-11-16

申请号：US15152794

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/66 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/4821 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1203

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US10157777B2

公开(公告)日：2018-12-18

申请号：US15152797

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84 ,  H01L23/66 ,  H01L29/786

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US20180145088A1

公开(公告)日：2018-05-24

申请号：US15355231

申请日：2016-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Mark D. Jaffe ,  John J. Pekarik

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76838 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/66477

Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.

公开(公告)号：US09673220B1

公开(公告)日：2017-06-06

申请号：US15065331

申请日：2016-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Randy L. Wolf ,  Mark D. Jaffe

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/78618

Abstract: Chip structures that include distributed wiring layouts and fabrication methods for forming such chip structures. A device structure is formed that includes a plurality of first device regions and a plurality of second device regions. A first wiring level is formed that includes a first wire coupled with the first device regions. A second wiring level is formed that includes a second wire coupled with the second device regions. The first wiring level is vertically separated from the second wiring level by a buried oxide layer of the silicon-on-insulator substrate.

公开(公告)号：US10712498B2

公开(公告)日：2020-07-14

申请号：US16216321

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G02B27/01 ,  A61B3/113 ,  G02B6/34 ,  G02B6/42 ,  G02F1/29 ,  G02F1/313 ,  G06K9/00 ,  G06K9/62 ,  G02B27/00 ,  G02F1/31 ,  G02B6/122 ,  G02B6/136 ,  G02B6/125 ,  G02B6/132 ,  G02B6/12 ,  G02B1/04

Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.

公开(公告)号：US10559743B2

公开(公告)日：2020-02-11

申请号：US15690828

申请日：2017-08-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H01L41/293 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H03H9/64 ,  G06F17/50 ,  H01L41/08 ,  H01L41/25 ,  H01L23/66 ,  H01L25/16 ,  H01L27/06 ,  H01L49/02

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.