公开(公告)号：US10242947B2

公开(公告)日：2019-03-26

申请号：US15713756

申请日：2017-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L21/76 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US20180012845A1

公开(公告)日：2018-01-11

申请号：US15713756

申请日：2017-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76251 ,  H01L21/76254 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US20180108566A1

公开(公告)日：2018-04-19

申请号：US15837279

申请日：2017-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/498 ,  H01L23/48 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

公开(公告)号：US09818637B2

公开(公告)日：2017-11-14

申请号：US14982576

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US09812404B2

公开(公告)日：2017-11-07

申请号：US14984547

申请日：2015-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael J. Shapiro ,  John A. Fitzsimmons ,  Natalia Borjemscaia

IPC: H01L21/70 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76898 ,  H01L22/14 ,  H01L23/528

Abstract: The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of manufacture. The structure includes: a conductive material; a dielectric material formed over the conductive material; a non-corrosive conductive material in at least one opening of the dielectric material and in direct contact with the conductive material; a crackstop structure formed over the dielectric material; and at least one of wiring layer in contact with the non-corrosive conductive material.

公开(公告)号：US09589806B1

公开(公告)日：2017-03-07

申请号：US14886424

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Huihang Dong ,  John A. Fitzsimmons

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/283 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: An IC structure including: a first replacement gate stack for the pFET, the first replacement gate stack including: an interfacial layer in a first opening in the dielectric layer; a high-k layer over the interfacial layer in the first opening; a pFET work function metal layer over the high-k layer in the first opening; and a first gate electrode layer over the pFET work function metal layer and substantially filling the first opening; and a second replacement gate stack for the nFET, the second gate stack laterally adjacent to the first gate stack and including: the interfacial layer in a second opening in the dielectric layer; the high-k layer over the interfacial layer in the second opening; a nFET work function metal layer over the high-k layer in the second opening; and a second gate electrode layer over the nFET work function metal layer and substantially filling the second opening.

Abstract translation: 一种IC结构，包括：用于pFET的第一替换栅极堆叠，所述第一替换栅极堆叠包括：在所述介电层中的第一开口中的界面层; 在第一开口的界面层上的高k层; 在第一开口中的高k层上的pFET功函数金属层; 以及在pFET功函数金属层上方的基本上填充第一开口的第一栅极电极层; 以及用于nFET的第二替代栅极堆叠，所述第二栅极堆叠横向邻近所述第一栅极堆叠并且包括：所述介电层中的第二开口中的界面层; 在第二开口的界面层上的高k层; 在第二开口的高k层上的nFET功函数金属层; 以及在nFET功函数金属层上方的第二栅电极层，并基本上填充第二开口。

公开(公告)号：US09461017B1

公开(公告)日：2016-10-04

申请号：US14685061

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Andrew H. Simon ,  Anthony K. Stamper

IPC: H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/66 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/66 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/8112 ,  H01L2224/8312 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14

Abstract: An electronic package comprising a plurality of vertically stacked integrated circuit (IC) devices including a first IC device and a second IC device is provided. The electronic package also includes a first bonding layer coupling one side of the first IC device entirely to a portion of a side of the second IC device. The remaining portion of the side of the second IC device that is not coupled to the one side of the first IC device, includes an antenna.

Abstract translation: 提供了一种包括多个垂直堆叠集成电路（IC）装置的电子封装，包括第一IC器件和第二IC器件。 电子封装还包括将第一IC器件的一侧完全耦合到第二IC器件的一侧的一部分的第一接合层。 第二IC器件的未耦合到第一IC器件的一侧的侧面的剩余部分包括天线。

公开(公告)号：US09966310B1

公开(公告)日：2018-05-08

申请号：US15837279

申请日：2017-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

公开(公告)号：US09852959B2

公开(公告)日：2017-12-26

申请号：US15017004

申请日：2016-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fitzsimmons ,  Michael J. Shapiro ,  Natalia Borjemscaia ,  Vincent McGahay

IPC: H01L23/26 ,  H01L23/535 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/26 ,  H01L23/3142 ,  H01L23/535 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/3025 ,  H01L2924/3512

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.

公开(公告)号：US20170186693A1

公开(公告)日：2017-06-29

申请号：US14982097

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/00 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76251 ,  H01L21/76852 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.