公开(公告)号：US20140154877A1

公开(公告)日：2014-06-05

申请号：US13689844

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了具有低电阻金属栅极结构的集成电路制造方法。 一种方法包括在FET区域中形成的FET沟槽中形成金属栅叠层。 金属栅极堆叠被蚀刻以形成凹陷的金属栅极堆叠和凹陷。 凹槽由FET区域中的侧壁限定，并设置在凹陷金属栅极堆叠的上方。 衬套形成在侧壁和凹入的金属门叠层之上，并且在凹槽中限定内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。

公开(公告)号：US20140021615A1

公开(公告)日：2014-01-23

申请号：US13770026

申请日：2013-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L23/532 ,  H01L23/538 ,  H01L21/02

CPC classification number: H01L23/53209 ,  H01L21/02697 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is generally directed to multi-layer barrier layer stacks for interconnect structures that may be used to reduce mechanical stress levels between the interconnect structure and a dielectric material layer in which the interconnect structure is formed. One illustrative method disclosed herein includes forming a recess in a dielectric layer of a substrate and forming an adhesion barrier layer including an alloy of tantalum and at least one transition metal other than tantalum to line the recess, wherein forming the adhesion barrier layer includes creating a first stress level across a first interface between the adhesion barrier layer and the dielectric layer. The method also includes forming a stress-reducing barrier layer including tantalum over the adhesion barrier layer, wherein the stress-reducing barrier layer reduces the first stress level to a second stress level less than the first stress level, and filling the recess with a fill layer.

Abstract translation: 本公开通常涉及用于互连结构的多层势垒层堆叠，其可用于减小互连结构与其中形成互连结构的介电材料层之间的机械应力水平。 本文公开的一种说明性方法包括在基底的电介质层中形成凹陷，并形成包括钽和至少一种不同于钽的过渡金属的合金的粘合阻挡层，以使凹槽成直线，其中形成粘合阻挡层包括形成 在粘合阻挡层和电介质层之间的第一界面上的第一应力水平。 该方法还包括在粘合阻挡层上形成包括钽的应力减小阻挡层，其中减小应力的阻挡层将第一应力水平降低到小于第一应力水平的第二应力水平，并且用填充物填充凹部 层。

公开(公告)号：US09142633B2

公开(公告)日：2015-09-22

申请号：US13714049

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Mark V. Raymond ,  Valli Arunachalam ,  Hoon Kim

IPC: H01L21/283 ,  H01L29/49 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4916 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括提供半导体衬底并在半导体衬底上形成翅片。 每个翅片形成有侧壁。 该方法还包括在每个翅片的侧壁上共形沉积金属膜堆叠。 在该方法中，金属膜堆叠被退火以在每个翅片的侧壁上形成金属硅化物膜。

公开(公告)号：US08691689B1

公开(公告)日：2014-04-08

申请号：US13689839

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L21/44

CPC classification number: H01L29/66575 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/665

Abstract: Methods for fabricating integrated circuits having low resistance device contacts are provided. One method includes depositing an ILD layer of insulating material overlying a device region that includes a metal silicide region. The ILD layer is etched to form a sidewall that defines a contact opening formed through the ILD layer exposing the metal silicide region. A liner is formed overlying the sidewall and the metal silicide region and defines an inner cavity in the contact opening. A copper layer is formed overlying the liner and at least partially filling the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了制造具有低电阻器件触点的集成电路的方法。 一种方法包括沉积覆盖在包括金属硅化物区域的器件区域上的绝缘材料的ILD层。 蚀刻ILD层以形成侧壁，其限定通过暴露金属硅化物区域的ILD层形成的接触开口。 衬垫形成在侧壁和金属硅化物区域上方并且限定了接触开口中的内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。

公开(公告)号：US09105497B2

公开(公告)日：2015-08-11

申请号：US14017485

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

公开(公告)号：US09076792B2

公开(公告)日：2015-07-07

申请号：US14287533

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L21/02 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/53209 ,  H01L21/02697 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess.

Abstract translation: 半导体器件包括限定在介电层中的凹部和限定在凹部中的互连结构。 所述互连结构包括衬在所述凹部中的第一阻挡层，所述第一阻挡层包括钽合金和除了钽之外的第一过渡金属，其中所述第一阻挡层和所述介电层之间的第一界面具有第一应力水平。 第二阻挡层位于第一阻挡层上，第二阻挡层包括钽和氮化钽中的至少一个，其中第二阻挡层和第一阻挡层之间的第二界面具有小于第二阻挡层的第二应力水平 第一压力水平。 互连结构还包括基本上填充凹部的填充材料。

公开(公告)号：US08778789B2

公开(公告)日：2014-07-15

申请号：US13689844

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L21/3205

CPC classification number: H01L29/66666 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了具有低电阻金属栅极结构的集成电路制造方法。 一种方法包括在FET区域中形成的FET沟槽中形成金属栅叠层。 金属栅极堆叠被蚀刻以形成凹陷的金属栅极堆叠和凹陷。 凹槽由FET区域中的侧壁限定，并设置在凹陷金属栅极堆叠的上方。 衬套形成在侧壁和凹入的金属门叠层之上，并且在凹槽中限定内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。

公开(公告)号：US08623758B1

公开(公告)日：2014-01-07

申请号：US13657182

申请日：2012-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76852 ,  H01L21/76858 ,  H01L2221/1078 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming an adhesion barrier layer over a dielectric layer formed on a substrate. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. A metal layer is formed over the stress-reducing barrier layer. The metal layer, adhesion barrier layer, and stress-reducing barrier layer define an interconnect metal stack. Recesses are defined in the interconnect metal stack to expose the dielectric layer. The recesses are filled with a dielectric material, wherein a portion of the interconnect metal stack disposed between adjacent recessed filled with dielectric material defines an interconnect structure.

Abstract translation: 一种方法包括在形成在基底上的电介质层上形成粘合阻挡层。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 在应力降低阻挡层上形成金属层。 金属层，粘合阻挡层和应力减小阻挡层限定互连金属叠层。 在互连金属叠层中限定凹陷以暴露电介质层。 这些凹部填充有电介质材料，其中设置在相邻凹陷的填充有电介质材料的互连金属叠层的一部分限定互连结构。

公开(公告)号：US20150061027A1

公开(公告)日：2015-03-05

申请号：US14017485

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

公开(公告)号：US09362283B2

公开(公告)日：2016-06-07

申请号：US14793005

申请日：2015-07-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Abstract translation: 集成电路产品包括具有栅极结构的NMOS晶体管，该栅极结构包括NMOS栅绝缘层，位于NMOS栅绝缘层上的第一NMOS金属层，位于第一NMOS金属层上方的NMOS金属硅化物材料， 位于NMOS栅极绝缘层上方并与NMOS栅绝缘层接触的第二金属材料，第一NMOS金属层和NMOS金属硅化物层。 PMOS晶体管具有栅极结构，其包括PMOS栅极绝缘层，位于PMOS栅极绝缘层上的第一PMOS金属层，位于第一PMOS金属层上方的PMOS金属硅化物材料和位于第一PMOS金属层上方的第二金属材料层 并且与PMOS栅绝缘层，第一PMOS金属层和PMOS金属硅化物层接触。