中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.018 seconds)

    Structure and method to reduce shorts and contact resistance in semiconductor devices
    1.
    发明授权
    Structure and method to reduce shorts and contact resistance in semiconductor devices 有权

    公开(公告)号：US10741495B2

    公开(公告)日：2020-08-11

    申请号：US15873946

    申请日：2018-01-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sunil K. Singh ,  Vinit O. Todi ,  Shao Beng Law

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

    Abstract: In an exemplary method, a first dielectric layer is formed on a substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is a carbon rich film and different from the first dielectric layer. A trench is formed through the first and second dielectric layers. A conductive line is formed in the trench. A third dielectric layer is formed on the second dielectric layer and conductive line. The material of the third dielectric layer is different from the second dielectric layer. A via opening is formed through the third dielectric layer and stops at the second dielectric layer with a portion of the conductive line exposed to the via opening. At the bottom of the via opening, a recess is formed in the second dielectric layer adjacent to the conductive line. The via opening and recess are filled with a conductive material contacting the conductive line.

    STRUCTURE AND METHOD TO REDUCE SHORTS AND CONTACT RESISTANCE IN SEMICONDUCTOR DEVICES
    2.
    发明申请
    STRUCTURE AND METHOD TO REDUCE SHORTS AND CONTACT RESISTANCE IN SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190221523A1

    公开(公告)日：2019-07-18

    申请号：US15873946

    申请日：2018-01-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sunil K. Singh ,  Vinit O. Todi ,  Shao Beng Law

    IPC: H01L23/532 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

    Abstract: In an exemplary method, a first dielectric layer is formed on a substrate. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is a carbon rich film and different from the first dielectric layer. A trench is formed through the first and second dielectric layers. A conductive line is formed in the trench. A third dielectric layer is formed on the second dielectric layer and conductive line. The material of the third dielectric layer is different from the second dielectric layer. A via opening is formed through the third dielectric layer and stops at the second dielectric layer with a portion of the conductive line exposed to the via opening. At the bottom of the via opening, a recess is formed in the second dielectric layer adjacent to the conductive line. The via opening and recess are filled with a conductive material contacting the conductive line.

    VIA AND SKIP VIA STRUCTURES
    5.
    发明申请
    VIA AND SKIP VIA STRUCTURES 审中-公开

    公开(公告)号：US20190021176A1

    公开(公告)日：2019-01-17

    申请号：US15647400

    申请日：2017-07-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

    IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

    Pre-spacer self-aligned cut formation
    7.
    发明授权
    Pre-spacer self-aligned cut formation 有权

    公开(公告)号：US09966338B1

    公开(公告)日：2018-05-08

    申请号：US15490181

    申请日：2017-04-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Shao Beng Law

    IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L21/76883 ,  H01L21/76804 ,  H01L21/7685

    Abstract: Methods of forming self-aligned cuts and structures formed with self-aligned cuts. A dielectric layer is formed on a metal hardmask layer, and a mandrel is formed on the dielectric layer. A cut is formed that extends through the dielectric layer to the metal hardmask layer. A section of a metal layer is formed on an area of the metal hardmask layer exposed by the cut in the dielectric layer. After the metal layer is formed, a spacer is formed on a vertical sidewall of the mandrel.

    Line end structures for semiconductor devices
    8.
    发明授权
    Line end structures for semiconductor devices 有权

    公开(公告)号：US10770392B1

    公开(公告)日：2020-09-08

    申请号：US16393973

    申请日：2019-04-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nicholas V. Licausi ,  Shao Beng Law

    IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: A method of fabricating a semiconductor device structure comprising depositing a layer of material on a dielectric stack and patterning the layer of material to form a hard mask, depositing a metal layer covering the hard mask to form a metal hard mask, forming vias in the dielectric stack using the metal hard mask, removing the metal hard mask, and forming trenches in the dielectric stack using the hard mask, wherein the hard mask and the metal hard mask are used to define a line end structure separating the trenches.

    Etch profile control during skip via formation
    9.
    发明授权
    Etch profile control during skip via formation 有权

    公开(公告)号：US10109526B1

    公开(公告)日：2018-10-23

    申请号：US15609408

    申请日：2017-05-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  J. Jay McMahon ,  Ryan S. Smith ,  Errol Todd Ryan ,  Shao Beng Law

    IPC: H01L21/768

    Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.

Patent Agency Ranking