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    RETROGRADE DOPED LAYER FOR DEVICE ISOLATION
    1.
    发明申请
    RETROGRADE DOPED LAYER FOR DEVICE ISOLATION 审中-公开
    用于设备隔离的重新布置层

    公开(公告)号：US20160035728A1

    公开(公告)日：2016-02-04

    申请号：US14882308

    申请日：2015-10-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

    IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

    CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

    Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。

    Fin pitch scaling and active layer isolation
    4.
    发明授权
    Fin pitch scaling and active layer isolation 有权
    鳍间距缩放和有源层隔离

    公开(公告)号：US09076842B2

    公开(公告)日：2015-07-07

    申请号：US14011125

    申请日：2013-08-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven John Bentley ,  Bartlomiej Jan Pawlak

    IPC: H01L21/302 ,  H01L21/764 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

    Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

    Abstract translation: 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。

    Self-aligned gate-first VFETs using a gate spacer recess
    5.
    发明授权
    Self-aligned gate-first VFETs using a gate spacer recess 有权
    使用栅极间隔凹槽的自对准栅极 - 第一VFET

    公开(公告)号：US09536793B1

    公开(公告)日：2017-01-03

    申请号：US15135917

    申请日：2016-04-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： John H. Zhang ,  Kwan-Yong Lim ,  Steven John Bentley ,  Chanro Park

    IPC: H01L29/786 ,  H01L21/8238

    CPC classification number: H01L21/823828 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823885

    Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed. Embodiments include providing a substrate including adjacent transistor regions; forming adjacent and spaced fin-structures each including hardmask over a fin and over a different transistor region; forming a gate-dielectric and metal-spacer consecutively on each side of each fin-structure; forming a liner on all exposed surfaces of the hardmask, gate-dielectrics, and metal-spacers and the substrate; forming an ILD filling spaces between the fin-structures and coplanar with an upper surface of the liner; removing the liner over the fin-structures; removing the hardmask and recessing the liner, the gate-dielectrics and metal-spacers of each fin-structure creating cavities in the ILD; forming a low-k spacer on sidewalls of and over the metal-spacers and liners in each cavity; forming a top S/D structure over the gate-dielectric and fin in each cavity; and forming a top S/D contact over each top S/D structure.

    Abstract translation: 公开了使用栅极 - 间隔物凹槽的自对准栅极 - 第一VFET和所得到的器件的方法。 实施例包括提供包括相邻晶体管区域的衬底; 形成相邻和间隔的翅片结构，每个翅片结构包括翅片上的硬掩模和不同的晶体管区域上的硬掩模; 在每个翅片结构的每一侧上连续形成栅电介质和金属间隔物; 在硬掩模，栅极 - 电介质和金属间隔物和基底的所有暴露表面上形成衬垫; 在翅片结构之间形成ILD填充空间并与衬套的上表面共面; 将衬垫移出翅片结构; 去除硬掩模并使衬垫凹陷，每个鳍结构的栅电介质和金属间隔件在ILD中产生空腔; 在每个腔中的金属间隔件和衬垫的侧壁上形成低k间隔物; 在每个腔中的栅电介质和鳍上形成顶部S / D结构; 并且在每个顶部S / D结构上形成顶部S / D接触。

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