公开(公告)号：US09337315B2

公开(公告)日：2016-05-10

申请号：US14157851

申请日：2014-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

Abstract: A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

公开(公告)号：US09337259B2

公开(公告)日：2016-05-10

申请号：US14154438

申请日：2014-01-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kerber ,  Ali Khakifirooz ,  Balasubramanian Pranatharthiharan

IPC: H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

Abstract: A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole.

Abstract translation: 改进ETSOI MOSFET器件的结构包括具有至少覆盖在第二半导体层上的氧化物层上的第一半导体层的区域的晶片。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔没有完全着陆，至少部分地延伸到STI中，并且绝缘材料沉积在孔中。

公开(公告)号：US09324797B2

公开(公告)日：2016-04-26

申请号：US14751761

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09190411B2

公开(公告)日：2015-11-17

申请号：US13914808

申请日：2013-06-11

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。

公开(公告)号：US20150140761A1

公开(公告)日：2015-05-21

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/266 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US20140374807A1

公开(公告)日：2014-12-25

申请号：US13921265

申请日：2013-06-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L29/66803

Abstract: Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an epitaxial layer minimizes punch through leakage whilst an epitaxial depositional process applies a cladding layer on the doped fins, the deposition resulting in a multigate device having improved device isolation.

Abstract translation: 本发明的方面涉及一种用于形成在硅衬底上具有一组散热片的集成电路的方法，该散热片组根据预定图案形成。 在沉积外延层之前用N型掺杂剂原位掺杂散热片使冲击穿孔最小化，而外延沉积工艺在掺杂的翅片上施加覆层，沉积导致具有改进的器件隔离的多器件装置。

公开(公告)号：US10199220B2

公开(公告)日：2019-02-05

申请号：US15652413

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US09793113B2

公开(公告)日：2017-10-17

申请号：US15075668

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/20 ,  H01L29/78 ,  H01L21/02 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/0243 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/31 ,  H01L21/311 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66446 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US09548356B2

公开(公告)日：2017-01-17

申请号：US14714779

申请日：2015-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kerber ,  Arvind Kumar ,  Shom Ponoth

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract translation: 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US09378972B2

公开(公告)日：2016-06-28

申请号：US14632313

申请日：2015-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Matthew E. Colburn ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/311 ,  H01L21/308 ,  H01L27/088 ,  H01L21/84 ,  H01L27/108 ,  H01L29/06 ,  H01L27/11

CPC classification number: H01L21/3086 ,  H01L21/3088 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/1104 ,  H01L29/0657

Abstract: Methods for forming semiconductor devices. Methods for forming fin structures include forming first sidewalls around a first set of mandrels. The first set of mandrels is removed and second sidewalls are formed around the first sidewalls and a second set of mandrels. The first sidewalls and the second set of mandrels are removed and an underlying layer around the second sidewalls is etched.

Abstract translation: 半导体器件形成方法。 形成翅片结构的方法包括围绕第一组心轴形成第一侧壁。 去除第一组心轴，并且在第一侧壁和第二组心轴周围形成第二侧壁。 去除第一侧壁和第二组心轴，并且蚀刻围绕第二侧壁的下层。