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    MANAGING DATA USING A NUMBER OF NON-VOLATILE MEMORY ARRAYS
    4.
    发明申请
    MANAGING DATA USING A NUMBER OF NON-VOLATILE MEMORY ARRAYS 审中-公开
    使用非易失性存储器阵列管理数据

    公开(公告)号：US20160350028A1

    公开(公告)日：2016-12-01

    申请号：US15113901

    申请日：2014-01-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B. LESARTRE ,  Martin FOLTIN

    IPC: G06F3/06

    CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0685 ,  G06F11/1441 ,  G06F12/08 ,  G06F12/0868 ,  Y02D10/13

    Abstract: A method for managing data using a number of non-volatile memory arrays is described. The method includes writing data from a volatile memory region to a first non-volatile memory array. The method also includes writing a remaining portion of the data from the volatile memory region to a second non-volatile memory array in response to detecting that an event has occurred. The second non-volatile memory array has a lower write latency than the first non-volatile memory array.

    Abstract translation: 描述了使用多个非易失性存储器阵列来管理数据的方法。 该方法包括将数据从易失性存储器区域写入第一非易失性存储器阵列。 该方法还包括响应于检测到事件已经发生而将数据的剩余部分从易失性存储器区域写入第二非易失性存储器阵列。 第二非易失性存储器阵列具有比第一非易失性存储器阵列更低的写入延迟。

    MANAGING A MULTI-LANE SERIAL LINK
    5.
    发明申请
    MANAGING A MULTI-LANE SERIAL LINK 审中-公开
    管理多个串行链路

    公开(公告)号：US20160328356A1

    公开(公告)日：2016-11-10

    申请号：US15108633

    申请日：2014-01-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B. LESARTRE ,  Martin FOLTIN

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/405 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A method for managing a multi-lane serial link is described. The method includes establishing a serial link between a number of integrated circuits across a first number of lanes. The first number of lanes are a subset of a number of available lanes on the serial link. The method also includes selecting to change a transmission state of a second number of lanes. The second number of lanes are a subset of the available lanes. The method also includes changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes. The method further includes synchronizing the first number of lanes and the second number of lanes.

    Abstract translation: 描述了一种用于管理多通道串行链路的方法。 该方法包括在多个通道之间的多个集成电路之间建立串行链路。 第一条车道是串行链路上可用车道数量的一个子集。 该方法还包括选择改变第二数量车道的传输状态。 第二条车道是可用车道的一个子集。 该方法还包括改变第二数量车道的传输状态，同时在多条剩余车道上传送数据。 该方法还包括同步第一数量的车道和第二车道数。

    SCALABLE MICROSERVICES-DRIVEN INDUSTRIAL IOT CONTROLLER ARCHITECTURE
    6.
    发明申请
    SCALABLE MICROSERVICES-DRIVEN INDUSTRIAL IOT CONTROLLER ARCHITECTURE 有权

    公开(公告)号：US20220276627A1

    公开(公告)日：2022-09-01

    申请号：US17186678

    申请日：2021-02-26

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Martin FOLTIN ,  William EDWARD WHITE ,  Aalap TRIPATHY ,  Harvey EDWARD WHITE, JR.

    IPC: G05B19/042 ,  G06F9/54

    Abstract: Systems and methods are provided for enabling coexistence of Information Technology (IT) systems and Operational Technology (OT) systems, where advanced computing functionality realized by the IT systems can be applied to legacy applications and incumbent hardware technologies resident in the OT systems. A distributed control node (DCN) implemented between the IT and OT systems may comprise a microcontroller system partitioned into two processor clusters. Microservices associated with the IT systems are provisioned to a high performance processor cluster, and legacy applications running bare metal associated with the OT systems are provisioned to a real-time processor cluster. Partitioning of the microcontroller system allows for interoperability between the microservices and the legacy applications.

    CONVOLUTIONAL NEURAL NETWORK
    7.
    发明申请
    CONVOLUTIONAL NEURAL NETWORK 有权

    公开(公告)号：US20210241068A1

    公开(公告)日：2021-08-05

    申请号：US17049032

    申请日：2018-04-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Martin FOLTIN ,  John Paul STRACHAN ,  Sergey SEREBRYAKOV

    IPC: G06N3/04 ,  G06N3/10 ,  G06N3/08

    Abstract: A convolutional neural network system includes a first part of the convolutional neural network comprising an initial processor configured to process an input data set and store a weight factor set in the first part of the convolutional neural network; and a second part of the convolutional neural network comprising a main computing system configured to process an export data set provided from the first part of the convolutional neural network.

    REFERENCE COLUMN SENSING FOR RESISTIVE MEMORY
    8.
    发明申请
    REFERENCE COLUMN SENSING FOR RESISTIVE MEMORY 审中-公开

    公开(公告)号：US20180301187A1

    公开(公告)日：2018-10-18

    申请号：US15768546

    申请日：2015-10-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： James S IGNOWSKI ,  Martin FOLTIN ,  Yoocharn JEON

    IPC: G11C13/00

    Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.

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