公开(公告)号：US10529394B2

公开(公告)日：2020-01-07

申请号：US16117509

申请日：2018-08-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Ali Shafiee Ardestani ,  Naveen Muralimanohar ,  Brent Buchanan

IPC: G11C7/16 ,  G11C7/22 ,  H03K21/02 ,  H03M1/34 ,  H03M1/66

Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

公开(公告)号：US20190065117A1

公开(公告)日：2019-02-28

申请号：US16073143

申请日：2016-03-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Ali Shafiee Ardestani

IPC: G06F3/06 ,  G06F17/30 ,  G11C13/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G06F16/2237 ,  G06F16/2379 ,  G06J1/00 ,  G06T1/60 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0002

Abstract: In an example, a method comprises receiving a first matrix of values to be mapped to a resistive memory array, wherein each value in the matrix is to be represented as a resistance of a resistive memory element. An outlying value may be identified in the first matrix. At least one value of a portion of the first matrix containing the outlying value may be substituted with at least one substitute value to form a substituted first matrix.

公开(公告)号：US20180373902A1

公开(公告)日：2018-12-27

申请号：US16063892

申请日：2016-01-21

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Ben Feinberg

IPC: G06G7/161 ,  G06G7/14 ,  G06F17/16 ,  H03M1/12 ,  G11C13/00

Abstract: A circuit includes an engine to compute analog multiplication results between vectors of a sub-matrix, An analog to digital converter (ADC) generates a digital value for the analog multiplication results computed by the engine. A shifter shifts the digital value of analog multiplication results a predetermined number of bits to generate a shifted result. An adder adds the shifted result to the digital value of a second multiplication result to generate a combined multiplication result.

公开(公告)号：US20180314927A1

公开(公告)日：2018-11-01

申请号：US15770430

申请日：2015-10-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  John Paul Strachan ,  Rajeev Balasubramonian ,  R. Stanley Williams

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/0635

Abstract: According to an example, a hybrid synaptic architecture based neural network may be implemented by determining, from input data, information that is to be recognized, mined, and/or synthesized by a plurality of analog neural cores. Further, the hybrid synaptic architecture based neural network may be implemented by determining, based on the information, selected ones of the plurality of analog neural cores that are to be actuated to identify a data subset of the input data to generate, based on the analysis of the data subset, results of the recognition, mining, and/or synthesizing of the information.

公开(公告)号：US20180307420A1

公开(公告)日：2018-10-25

申请号：US16011187

申请日：2018-06-18

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Doe Hyun Yoon ,  Naveen Muralimanohar ,  Jichuan Chang ,  Parthasarathy Ranganathan

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/108 ,  G06F2211/1054 ,  G06F2211/1066

Abstract: An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

公开(公告)号：US10019176B2

公开(公告)日：2018-07-10

申请号：US14417220

申请日：2012-10-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Doe Hyun Yoon ,  Naveen Muralimanohar ,  Jichuan Chang ,  Parthasarathy Ranganathan

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/108 ,  G06F2211/1054 ,  G06F2211/1066

Abstract: An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

公开(公告)号：US20180004708A1

公开(公告)日：2018-01-04

申请号：US15201040

申请日：2016-07-01

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Ben Feinberg ,  Ali Shafiee-Ardestani

IPC: G06F17/16 ,  H03M1/66 ,  H03M1/12

CPC classification number: G06F17/16 ,  G06G7/16 ,  H03M1/12 ,  H03M1/66

Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

公开(公告)号：US20170357463A1

公开(公告)日：2017-12-14

申请号：US15181541

申请日：2016-06-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Cullen E. Bash

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0616 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/3058 ,  G06F12/02 ,  G11C7/04

Abstract: An example device in accordance with an aspect of the present disclosure includes a characterization engine and an allocation engine. The characterization engine is to receive information and characterizes expected temperature exposure of a memory device, to store a characterization profile of a plurality of memory devices of a computing system. The characterization engine is to refer to the characterization profile to identify the expected temperature exposure for a given memory device.

公开(公告)号：US20170287540A1

公开(公告)日：2017-10-05

申请号：US15507790

申请日：2014-09-25

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Amit S. Sharma ,  Gary Gibson ,  Erik Ordentlich ,  Naveen Muralimanohar

IPC: G11C8/10 ,  G11C13/00

CPC classification number: G11C8/10 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028

Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.

公开(公告)号：US20170220256A1

公开(公告)日：2017-08-03

申请号：US15500594

申请日：2015-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rajeev Balasubramonian ,  Paolo Faraboschi ,  Gregg B. Lesartre ,  Naveen Muralimanohar

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/0238 ,  G06F12/1408 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7208 ,  G11C29/52 ,  Y02D10/13

Abstract: Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.