公开(公告)号：US06475859B1

公开(公告)日：2002-11-05

申请号：US09593287

申请日：2000-06-13

申请人： Helmut Horst Tews ,  Brian S. Lee ,  Joachim Hoepfner

发明人： Helmut Horst Tews ,  Brian S. Lee ,  Joachim Hoepfner

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L21/2236 ,  H01L28/84

摘要： A method of doping trench sidewall and hemispherical-grained silicon in deep trench cells to increase surface area and storage capacitance while avoiding deformation of trenches and hemispherical-grained silicon, comprising: a) Etching a deep trench structure by reactive ion etching; b) Forming a LOCOS collar in an upper portion of the trench over a conformal layer of a silicon containing material, the collar leaving a lower portion of the trench exposed; c) Depositing a film of hemispherical-grained silicon (HSG-Si) at sidewalls of the deep trench; d) Plasma doping the hemispherical-grained silicon; and e) Depositing a node dielectric and filling the trench with polysilicon.

摘要翻译： 一种在深沟槽单元中掺杂沟槽侧壁和半球晶硅的方法，以增加表面面积和存储电容，同时避免沟槽和半球晶硅的变形，包括：a）通过反应离子蚀刻蚀刻深沟槽结构; b）形成 在包含硅的材料的保形层上的沟槽上部的LOCOS环，所述套环暴露出沟槽的下部; c）在半导体衬底的侧壁处沉积半球形硅（HSG-Si）的膜 深沟槽; d）等离子体掺杂半球形硅; 安装）沉积节点电介质并用多晶硅填充沟槽。

公开(公告)号：US06372567B1

公开(公告)日：2002-04-16

申请号：US09553708

申请日：2000-04-20

申请人： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening

发明人： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening

IPC分类号： H01L218238

CPC分类号： H01L21/28211 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10864 ,  H01L27/10873 ,  H01L29/045

摘要： Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.

摘要翻译： 在DRAM中制备垂直晶体管结构的改进方法，其中沟槽顶部氧化物将底部存储电容器与开关晶体管分离，并且其中沟槽的上部在其侧壁处包含垂直晶体管，以获得均匀的栅极氧化 沟槽内的所有不同的晶面，使得均匀的厚度与晶体取向无关，包括：a）使晶片沟槽侧壁进行离子轰击足以产生氧化物侧壁的非晶层的时间; 和b）在氧化气氛中加热由步骤（a）得到的晶片，以引起非晶层的氧化和重结晶。

公开(公告)号：US06426253B1

公开(公告)日：2002-07-30

申请号：US09576465

申请日：2000-05-23

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L21/76237 ,  H01L21/823487 ,  H01L27/10841 ,  H01L27/10867

摘要： A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

摘要翻译： 使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。 电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。 低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。 然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。 然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或在沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分 沟槽暴露进一步加工。 或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。 自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

公开(公告)号：US06362040B1

公开(公告)日：2002-03-26

申请号：US09501502

申请日：2000-02-09

申请人： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening ,  Raj Jammy ,  John Faltermeier

发明人： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening ,  Raj Jammy ,  John Faltermeier

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L27/10876

摘要： A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer. The second dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness and the second thickness of the second dielectric layer are closer in thickness than the first thickness and the second thickness of the first dielectric layer due to the implantation of the dopants.

摘要翻译： 根据本发明的用于在衬底上生长电介质层的方法包括以下步骤：提供具有至少两个结晶面的衬底，所述晶体面由于至少两个晶面而具有不同的介电层生长速率。 在至少两个晶面上生长第一介电层，使得第一介电层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。 第一厚度比第一电介质层的第二厚度厚。 通过第一介电层注入掺杂剂。 通过第二厚度将更多数量的掺杂剂注入到衬底中，而不是通过第一介电层的第一厚度。 然后去除第一介电层。 在与去除的第一介电层相同的位置处生长第二介电层。 第二电介质层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。 由于掺杂剂的注入，第二介电层的第一厚度和第二厚度比第一厚度和第一介电层的第二厚度更厚。

公开(公告)号：US06335247B1

公开(公告)日：2002-01-01

申请号：US09597389

申请日：2000-06-19

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

IPC分类号： H01L21336

CPC分类号： H01L27/10864 ,  H01L27/10876

摘要： A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

摘要翻译： 一种使用选择性湿蚀刻在集成电路中形成垂直取向器件的方法，以仅去除深沟槽中的一部分侧壁，以及由此形成的器件。 虽然沟槽周边的一部分（例如，隔离环304）被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的衬底 侧壁（324）与单晶面。 单侧垂直沟槽晶体管可以形成在平坦侧壁上。 形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。 此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

公开(公告)号：US20110278680A1

公开(公告)日：2011-11-17

申请号：US13193692

申请日：2011-07-29

申请人： Helmut Horst Tews ,  Andre Schenk

发明人： Helmut Horst Tews ,  Andre Schenk

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.

摘要翻译： 在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。 栅电极与半导体本体电绝缘。 沿着栅电极的侧壁形成第一侧壁间隔物。 邻近第一侧壁间隔件形成牺牲侧壁间隔物。 牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。 平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。 然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。 所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。 然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

公开(公告)号：US20100330771A1

公开(公告)日：2010-12-30

申请号：US12876866

申请日：2010-09-07

申请人： Hans-Joachim Barth ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Helmut Horst Tews

IPC分类号： H01L21/02

CPC分类号： H01L28/75 ,  G06F17/5068 ,  H01L21/76897 ,  H01L22/14 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/562 ,  H01L23/585 ,  H01L27/0611 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.

摘要翻译： 公开了在半导体部件上形成防潮电容器的结构和方法。 电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

公开(公告)号：US07157328B2

公开(公告)日：2007-01-02

申请号：US11047312

申请日：2005-01-31

申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

IPC分类号： H01L21/8242

CPC分类号： H01L21/30604 ,  H01L29/66181

摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

公开(公告)号：US06967147B1

公开(公告)日：2005-11-22

申请号：US09714356

申请日：2000-11-16

申请人： Helmut Horst Tews ,  Jochen Beintner

发明人： Helmut Horst Tews ,  Jochen Beintner

IPC分类号： H01L20060101 ,  H01L21/265 ,  H01L21/28 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06

CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/10873 ,  Y10S438/981

摘要： Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.

摘要翻译： 用于通过使用氮注入并入不同厚度的栅极氧化物来形成用于DRAMS的双栅极氧化物的工艺。 使用倾斜的氮气注入或氮化物间隔物来产生“阴影效应”或区域，这限制了接近有效区域边缘的氮剂量。 氮剂量的减少导致在与浅沟槽相邻的有源区（AA）处的栅极氧化物厚度增加，增加了寄生角装置的阈值并且减小了副Vt（阈值电压）和结漏电。

公开(公告)号：US06677197B2

公开(公告)日：2004-01-13

申请号：US10032040

申请日：2001-12-31

申请人： Stephan Kudelka ,  Helmut Horst Tews

发明人： Stephan Kudelka ,  Helmut Horst Tews

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L29/66181

摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.

摘要翻译： 在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a） 在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模 衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物 在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物 进行多化学机械抛光。