中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.009 seconds)

    System for expanded detection and correction of errors in parallel binary data produced by data tracks
    1.
    发明授权
    System for expanded detection and correction of errors in parallel binary data produced by data tracks 失效
    数据跟踪产生的并行二进制数据中扩展检测和纠正错误的系统

    公开(公告)号：US3675200A

    公开(公告)日：1972-07-04

    申请号：US3675200D

    申请日：1970-11-23

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS C ,  HENLE ROBERT A ,  HSIAO MU Y ,  MALEY GERALD A ,  PRICER W DAVID

    IPC: G06F11/10 ,  G11C29/00 ,  G06F11/08 ,  G06K5/00

    CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C29/003

    Abstract: Errors in parallel binary data produced by a plurality of data track, e.g., a plurality of parallel shift registers, are corrected by a system in which the shift registers which are stuck, i.e., inalterable, are determined and counted. By single Hamming error detection means, the presence of a Hamming error and an indication of the bit position of a single Hamming error is made. Comparison means determine if the indicated Hamming error is coincident with a stuck track. Then, dependent on the parity condition of the data as well as the count of stuck tracks, apparatus is provided for complementing one or more of the stuck tracks and/or correcting the indicated Hamming error.

    Abstract translation: 由多个数据磁道（例如多个并行移位寄存器）产生的并行二进制数据的错误由其中确定并计数被卡住的，即不可更改的移位寄存器的系统来校正。 通过单个汉明误差检测装置，进行汉明误差的存在和单个汉明误差的比特位置的指示。 比较装置确定所指示的汉明误差是否与卡盘轨迹一致。 然后，依赖于数据的奇偶校验条件以及卡盘轨迹的计数，提供装置用于补充一个或多个卡住轨迹和/或校正所指示的汉明误差。

    Alterable-latent image monolithic memory
    2.
    发明授权
    Alterable-latent image monolithic memory 失效
    可更改的图像单片存储器

    公开(公告)号：US3662351A

    公开(公告)日：1972-05-09

    申请号：US3662351D

    申请日：1970-03-30

    Applicant: IBM

    Inventor： HO IRVING T ,  MALEY GERALD A ,  WAXMAN RONALD

    IPC: G11C7/20 ,  G11C11/411 ,  G11C16/04 ,  G11C17/08 ,  H01L27/10 ,  H01L27/105 ,  H03K3/356 ,  G11C11/00 ,  G11C17/00

    CPC classification number: H03K3/356008 ,  G11C7/20 ,  G11C11/4116 ,  G11C16/0466 ,  G11C17/08 ,  H01L27/10 ,  H01L27/105

    Abstract: A monolithic latent image memory is one having a plurality of bistable memory cells. Selected bistable memory cells include AC impedance means which are responsive at the transition from nonsustaining voltage level to an operating level so as to set the selected memory cells to a first predetermined state and thus provide a monolithic memory which is capable of functioning in a read-only and a read-write mode. The read-only state is selectively alterable by employing an AC impedance means which is multi-valued.

    Abstract translation: 单片潜像存储器是具有多个双稳态存储单元的潜像存储器。 所选择的双稳态存储器单元包括AC阻抗装置，其在从非维持电压电平转换到工作电平时响应，以便将所选择的存储器单元设置为第一预定状态，从而提供能够在 只读和读写模式。 通过使用多值的AC阻抗装置可选地改变只读状态。

    Ternary read-only memory
    4.
    发明授权
    Ternary read-only memory 失效
    第三版只读存储器

    公开(公告)号：US3656117A

    公开(公告)日：1972-04-11

    申请号：US3656117D

    申请日：1971-02-05

    Applicant: IBM

    Inventor： MALEY GERALD A ,  WALSH JAMES L

    IPC: G11C11/56 ,  G11C17/08 ,  G11C17/00 ,  G11C11/40

    CPC classification number: G11C11/5692 ,  G11C11/56 ,  G11C17/08

    Abstract: A ternary read-only memory comprises a matrix of transistors arranged in rows and columns. A plurality of bit lines are each connected to the transistors of a respective one of the columns. Connected to the emitter of each transistor is an impedance which may be either a diode, a conductive shunt or an open circuit. A word amplifier is connected to each row of transistors. Means are provided for energizing one of the bit lines and one of the word amplifiers so as to select one transistor for reading out. Each word amplifier includes means for generating a ternary logic function depending upon the value of the impedance connected to the emitter of the transistor selected by energization of the respective bit line and word amplifiers.

    Abstract translation: 三进制只读存储器包括以行和列排列的晶体管矩阵。 多个位线各自连接到相应一个列的晶体管。 连接到每个晶体管的发射极是阻抗，其可以是二极管，导电分路或开路。 字放大器连接到每行晶体管。 提供了用于激励位线之一和一个字放大器以便选择一个用于读出的晶体管的装置。 每个字放大器包括用于根据连接到通过相应位线和字放大器通电选择的晶体管的发射极的阻抗的值产生三元逻辑功能的装置。

    Auto-reset ternary latch
    7.
    发明授权
    Auto-reset ternary latch 失效
    自动复位三重锁

    公开(公告)号：US3671764A

    公开(公告)日：1972-06-20

    申请号：US3671764D

    申请日：1971-02-05

    Applicant: IBM

    Inventor： MALEY GERALD A ,  WALSH JAMES L

    IPC: H03K3/29 ,  H03K19/00 ,  H03K3/14

    CPC classification number: H03K3/29

    Abstract: An auto-reset ternary latch has a data input line, a gate line and an output line. Each of said lines is adapted to assume any one of three potential levels. When the potential of the gate is lowered from the uppermost level to an intermediate level, the potential of the output line moves up or down one level to an intermediate value. When the potential of the gate is lowered all the way to the lowermost level, the potential of the output line matches that of the data input line. The potential of the output line is maintained at said value when the potential of the gate line is thereafter raised.

    Abstract translation: 自动复位三进制锁存器具有数据输入线，栅极线和输出线。 所述线中的每一条适于承担三个电位电平中的任何一个。 当门的电位从最高电平降低到中间电平时，输出线的电位向上或向下移动一级到中间值。 当门的电位一直下降到最低电平时，输出线的电位与数据输入线的电位相匹配。 当栅极线的电位此后升高时，输出线的电位保持在所述值。

Patent Agency Ranking