公开(公告)号：US09171904B2

公开(公告)日：2015-10-27

申请号：US14086486

申请日：2013-11-21

Applicant: IMEC

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L21/77 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract translation: 提供FinFET器件和制造FinFET器件的方法。 示例性装置可以包括包括至少两个翅片结构的基板。 所述至少两个翅片结构中的每一个可以与源极和漏极区域接触，并且所述至少两个鳍结构中的每一个可以包括覆盖并与衬底接触的应变松弛缓冲器（SRB），并且上层覆盖和 与SRB联系。 可以选择上层和SRB的组成，使得第一鳍结构的上层在生长状态下经受第一迁移率增强应变，第一迁移率增强应变沿纵向施加于 源极区到漏极区，并且其中第二鳍结构的上层的至少上部被应变松弛。

公开(公告)号：US20170040168A1

公开(公告)日：2017-02-09

申请号：US15333995

申请日：2016-10-25

Applicant: IMEC

Inventor： Benjamin Vincent ,  Voon Yew Thean ,  Liesbeth Witters

IPC: H01L21/02 ,  C30B25/04 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  C30B23/04 ,  C30B19/12

CPC classification number: H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.

Abstract translation: 公开了用于外延生长基本上无缺陷的半导体材料的方法和掩模结构。 在一些实施例中，掩模结构包括限定延伸穿过第一层的第一沟槽的第一层，其中第一沟槽的底部由半导体衬底限定，第二层位于第一层的顶部，其中第二层限定 多个相对于第一沟槽非零角度定位的第二沟槽。

公开(公告)号：US09476143B2

公开(公告)日：2016-10-25

申请号：US13768462

申请日：2013-02-15

Applicant: IMEC

Inventor： Benjamin Vincent ,  Voon Yew Thean ,  Liesbeth Witters

IPC: C30B25/04 ,  C30B23/04 ,  H01L21/02 ,  H01L29/66 ,  C30B19/00

CPC classification number: H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.

Abstract translation: 公开了用于外延生长基本上无缺陷的半导体材料的方法和掩模结构。 在一些实施例中，该方法可以包括提供包括第一晶体材料的基底，其中第一晶体材料具有第一晶格常数; 在所述衬底上提供掩模结构，其中所述掩模结构包括第一层，所述第一层包括延伸穿过所述第一层的第一开口（其中所述第一开口的底部包括所述衬底），以及在所述第一层的顶部上的第二层， 第二级包括相对于第一开口非零角度定位的多个第二沟槽。 该方法还可以包括在第一开口的底部上外延生长第二晶体材料，其中第二晶体材料具有不同于第一晶格常数的第二晶格常数，并且第二晶体材料中的缺陷被捕获在第一开口中。

公开(公告)号：US10309925B2

公开(公告)日：2019-06-04

申请号：US15143262

申请日：2016-04-29

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Voon Yew Thean

IPC: G01N27/414 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules.

公开(公告)号：US20160320336A1

公开(公告)日：2016-11-03

申请号：US15143262

申请日：2016-04-29

Applicant: IMEC VZW

Inventor： Nadine COLLAERT ,  Voon Yew Thean

IPC: G01N27/414 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265

CPC classification number: G01N27/4145 ,  G01N27/414 ,  H01L21/26586 ,  H01L29/42356 ,  H01L29/6653

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及半导体器件，例如配置用于生物分子感测的场效晶体管器件。 一方面，半导体芯片包括至少一个场效应晶体管器件，其包括源极，漏极，栅极堆叠以及形成在源极和漏极之间的沟道区。 栅极堆叠仅部分地与源极侧和/或漏极侧的沟道区重叠，从而形成源极侧和/或在漏极侧的非重叠沟道区，其中非重叠沟道区 被配置用于感测生物分子。

公开(公告)号：US20140151766A1

公开(公告)日：2014-06-05

申请号：US14086486

申请日：2013-11-21

Applicant: IMEC

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract translation: 提供FinFET器件和制造FinFET器件的方法。 示例性装置可以包括包括至少两个翅片结构的基板。 所述至少两个翅片结构中的每一个可以与源极和漏极区域接触，并且所述至少两个鳍结构中的每一个可以包括覆盖并与衬底接触的应变松弛缓冲器（SRB），并且上层覆盖和 与SRB联系。 可以选择上层和SRB的组成，使得第一鳍结构的上层在生长状态下经受第一迁移率增强应变，第一迁移率增强应变沿纵向施加于 源极区到漏极区，并且其中第二鳍结构的上层的至少上部被应变松弛。

公开(公告)号：US10340139B2

公开(公告)日：2019-07-02

申请号：US15333995

申请日：2016-10-25

Applicant: IMEC

Inventor： Benjamin Vincent ,  Voon Yew Thean ,  Liesbeth Witters

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  C30B25/04 ,  C30B23/04 ,  C30B19/12 ,  C30B19/00

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.

公开(公告)号：US10211312B2

公开(公告)日：2019-02-19

申请号：US15230289

申请日：2016-08-05

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Voon Yew Thean

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.

公开(公告)号：US20170040331A1

公开(公告)日：2017-02-09

申请号：US15230289

申请日：2016-08-05

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Voon Yew Thean

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L21/0242 ,  H01L21/02425 ,  H01L21/02568 ,  H01L21/28291 ,  H01L29/6684 ,  H01L29/78391

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及非挥发性铁电存储器件及其制造方法。 一方面，非易失性存储器件包括半导体衬底上的高介电常数层（高k）层或金属层。 非易失性存储器件还包括插入在高k层或金属层与铁电层之间的二维（2D）半导体沟道层。 非易失性存储器件还包括在铁电层上的金属栅极层，并且还包括电源耦合到2D半导体沟道层的源极区域和漏极区域。

公开(公告)号：US09368498B2

公开(公告)日：2016-06-14

申请号：US14878012

申请日：2015-10-08

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.