公开(公告)号：US11088263B2

公开(公告)日：2021-08-10

申请号：US16893233

申请日：2020-06-04

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Geert Eneman

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/417

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion. The method additionally comprises forming on the channel portion an epitaxial semiconductor stressor layer enclosing the channel portion, wherein the stressor layer and the channel portion are lattice mismatched, forming an insulating layer and a sacrificial structure, wherein the sacrificial structure encloses the channel portion with the stressor layer formed thereon and wherein the insulating layer embeds the semiconductor structure and the sacrificial structure, forming in the insulating layer an opening exposing a surface portion of the sacrificial structure, and etching the sacrificial structure through the opening in the insulating layer, thereby forming a cavity exposing the stressor layer enclosing the channel portion. The method further comprises, subsequent to etching the sacrificial structure, etching the stressor layer in the cavity, and subsequent to etching the stressor layer, forming a gate stack in the cavity, wherein the gate stack encloses the channel portion of the vertical semiconductor structure.

公开(公告)号：US09171904B2

公开(公告)日：2015-10-27

申请号：US14086486

申请日：2013-11-21

Applicant: IMEC

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L21/77 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract translation: 提供FinFET器件和制造FinFET器件的方法。 示例性装置可以包括包括至少两个翅片结构的基板。 所述至少两个翅片结构中的每一个可以与源极和漏极区域接触，并且所述至少两个鳍结构中的每一个可以包括覆盖并与衬底接触的应变松弛缓冲器（SRB），并且上层覆盖和 与SRB联系。 可以选择上层和SRB的组成，使得第一鳍结构的上层在生长状态下经受第一迁移率增强应变，第一迁移率增强应变沿纵向施加于 源极区到漏极区，并且其中第二鳍结构的上层的至少上部被应变松弛。

公开(公告)号：US20140054547A1

公开(公告)日：2014-02-27

申请号：US13914514

申请日：2013-06-10

Applicant: GLOBALFOUNDRIES Inc. ,  IMEC

Inventor： Geert Eneman ,  David Brunco ,  Geert Hellings

IPC: H01L29/78

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L29/7781

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract translation: 所公开的技术涉及具有用于载流子限制的应变量子阱的晶体管及其制造方法。 在一个方面，FinFET或平面FET器件包括半导体衬底，形成在半导体衬底上的Ge的应变松弛缓冲层，形成在应变弛缓缓冲层上的沟道层和包含SiGe的应变量子势垒层 介于与应变松弛缓冲层和沟道层接触之间。 应变松弛缓冲层，应变量子势垒层和沟道层的组成被选择为使得沟道层的带偏移和应变量子势垒层的带偏移相对于应变松弛具有相反的符号 缓冲层。

公开(公告)号：US20240178051A1

公开(公告)日：2024-05-30

申请号：US18524355

申请日：2023-11-30

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Rongmei Chen ,  An De Keersgieter ,  Geert Eneman ,  Philippe Matagne

IPC: H01L21/74 ,  H01L21/768

CPC classification number: H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/823431

Abstract: A method includes: forming a structure on a frontside of a substrate, the structure including a first and a second source/drain body located in a first and a second source/drain region, respectively, and a channel body including a channel layer extending between the first and second source/drain bodies; forming a trench beside the first source/drain region by etching the substrate such that a lower portion of the trench undercuts the first source/drain region; forming a liner on the trench; forming an opening in the liner underneath the first source/drain region; and forming a dummy interconnect in the trench; where the method further includes exposing the dummy interconnect from a backside of the substrate; removing the dummy interconnect selectively to the liner; and forming a buried interconnect of a conductive material in the trench, where the buried interconnect is connected to the first source/drain body via the opening in the liner.

公开(公告)号：US20210336057A1

公开(公告)日：2021-10-28

申请号：US17241318

申请日：2021-04-27

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Basoene Briggs ,  An De Keersgieter ,  Anabela Veloso ,  Paola Favia

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.

公开(公告)号：US20170033183A1

公开(公告)日：2017-02-02

申请号：US15218922

申请日：2016-07-25

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer ,  Geert Eneman

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/161 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L21/324

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02469 ,  H01L21/02513 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42356 ,  H01L29/775

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

Abstract translation: 本文公开了一种半导体结构，其包括：（i）具有顶表面的单晶衬底，（ii）覆盖在单晶衬底上的非晶体结构，并且包括具有小于10微米的宽度的开口，并暴露部分顶部表面的 单晶衬底。 半导体结构还包括（iii）具有邻接部分的底表面的缓冲结构和每平方厘米具有小于108个穿透位错的顶表面，该缓冲结构由具有第一晶格常数的材料制成。 半导体结构还包括（iv）邻接缓冲结构的一个或多个IV族单晶结构，并且由具有与第一晶格常数不同的第二晶格常数的材料制成。

公开(公告)号：US20140170837A1

公开(公告)日：2014-06-19

申请号：US14106699

申请日：2013-12-13

Applicant: IMEC

Inventor： Benjamin Vincent ,  Geert Eneman

IPC: H01L21/322

CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

Abstract translation: 公开了一种用于从有源层减少缺陷的方法。 有源层可以是半导体器件中的半导体的一部分。 有源层可以至少由隔离结构侧向限定，并且可以在接触界面物理地接触隔离结构。 隔离结构和有源层可以邻接在共同的基本平坦的表面上。 该方法可以包括在共同的基本上平坦的表面上提供图案化的应力诱导层。 应力诱导层可以适于在活性层中诱导应力场，并且感应应力场可能导致活性层中缺陷的剪切应力。 该方法还可以包括在将图案化的应力诱导层提供在共同的基本平坦的表面上之后执行退火步骤。 该方法可以另外包括从共同的基本平坦的表面去除图案化的应力诱导层。

公开(公告)号：US08698129B2

公开(公告)日：2014-04-15

申请号：US13723149

申请日：2012-12-20

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Geert Hellings ,  Geert Eneman

IPC: H01L29/06

CPC classification number: H01L29/7782 ,  H01L29/0623 ,  H01L29/36

Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.

Abstract translation: 一种无植入物量子阱晶体管，其中所述掺杂区域包括相对于所述衬底的相邻区域的掺杂剂的浓度具有增加的掺杂剂浓度的注入区域，所述注入区域基本上位于所述量子阱区域的相对侧 门区域。

公开(公告)号：US20130161588A1

公开(公告)日：2013-06-27

申请号：US13723149

申请日：2012-12-20

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U.LEUVEN R&D

Inventor： Geert Hellings ,  Geert Eneman

IPC: H01L29/775 ,  H01L29/66

CPC classification number: H01L29/7782 ,  H01L29/0623 ,  H01L29/36

Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.

Abstract translation: 一种无植入物量子阱晶体管，其中所述掺杂区域包括相对于所述衬底的相邻区域的掺杂剂的浓度具有增加的掺杂剂浓度的注入区域，所述注入区域基本上位于所述量子阱区域的相对侧 门区域。

公开(公告)号：US20190081156A1

公开(公告)日：2019-03-14

申请号：US16119132

申请日：2018-08-31

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Geert Eneman ,  Nadine Collaert ,  Erik Rosseel

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

Abstract: A device and method for forming a vertical channel device is disclosed. The method includes: forming a vertical semiconductor pillar on a substrate, the vertical semiconductor pillar including a first pillar section, a second pillar section and a third pillar section, wherein the second pillar section is arranged between the first pillar section and the third pillar section and wherein the second pillar section is formed of a material being different from a material forming an upper portion of the first pillar section and different from a material forming a lower portion of the third pillar section; forming a spacer layer on a peripheral surface of the upper portion of the first pillar section and on a peripheral surface of the lower portion of the third pillar section; and forming a gate stack embedding the second pillar section and said upper portion of the first pillar section and said lower portion of the third pillar section, wherein the spacer layer forms a spacer between the gate stack and said upper portion of the first pillar section and between the gate stack and said lower portion of the third pillar section.