公开(公告)号：US20140170837A1

公开(公告)日：2014-06-19

申请号：US14106699

申请日：2013-12-13

Applicant: IMEC

Inventor： Benjamin Vincent ,  Geert Eneman

IPC: H01L21/322

CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

Abstract translation: 公开了一种用于从有源层减少缺陷的方法。 有源层可以是半导体器件中的半导体的一部分。 有源层可以至少由隔离结构侧向限定，并且可以在接触界面物理地接触隔离结构。 隔离结构和有源层可以邻接在共同的基本平坦的表面上。 该方法可以包括在共同的基本上平坦的表面上提供图案化的应力诱导层。 应力诱导层可以适于在活性层中诱导应力场，并且感应应力场可能导致活性层中缺陷的剪切应力。 该方法还可以包括在将图案化的应力诱导层提供在共同的基本平坦的表面上之后执行退火步骤。 该方法可以另外包括从共同的基本平坦的表面去除图案化的应力诱导层。

公开(公告)号：US20140077332A1

公开(公告)日：2014-03-20

申请号：US14024820

申请日：2013-09-12

Applicant: GLOBALFOUNDRIES Inc. ,  IMEC

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Brunco

IPC: H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

Abstract translation: 本发明涉及一种带状工程半导体器件，其包括衬底，突出结构，其形成在衬底中的凹部中并且在凹部上方延伸，具有掩埋部分和延伸部分，并且其中至少延伸部分包括 具有倒置“V”带隙分布的半导体材料，带隙值从该结构的横向边缘处的第一值逐渐增加到高于该结构的中心的第二值。 本发明还涉及这种带状工程半导体器件的制造方法。

公开(公告)号：US09171904B2

公开(公告)日：2015-10-27

申请号：US14086486

申请日：2013-11-21

Applicant: IMEC

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L21/77 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract translation: 提供FinFET器件和制造FinFET器件的方法。 示例性装置可以包括包括至少两个翅片结构的基板。 所述至少两个翅片结构中的每一个可以与源极和漏极区域接触，并且所述至少两个鳍结构中的每一个可以包括覆盖并与衬底接触的应变松弛缓冲器（SRB），并且上层覆盖和 与SRB联系。 可以选择上层和SRB的组成，使得第一鳍结构的上层在生长状态下经受第一迁移率增强应变，第一迁移率增强应变沿纵向施加于 源极区到漏极区，并且其中第二鳍结构的上层的至少上部被应变松弛。

公开(公告)号：US09029217B1

公开(公告)日：2015-05-12

申请号：US14592412

申请日：2015-01-08

Applicant: IMEC ,  GlobalFoundries Inc.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L21/336 ,  H01L29/94 ,  H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract translation: 本公开涉及一种带状工程半导体器件，其包括衬底和形成在衬底中的凹部中的突出结构。 突出结构在凹部上方延伸并具有埋设部分和延伸部分。 至少延伸部分包括具有倒置的“V”带隙轮廓的半导体材料，带隙值从结构的横向边缘处的第一值逐渐增加到高于第一值的第二值，高于第一值 结构。 本公开还涉及制造这种带状工程半导体器件的方法。

公开(公告)号：US20150126010A1

公开(公告)日：2015-05-07

申请号：US14592412

申请日：2015-01-08

Applicant: IMEC ,  GLOBALFOUNDRIES INC.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract translation: 本公开涉及一种带状工程半导体器件，其包括衬底和形成在衬底中的凹部中的突出结构。 突出结构在凹部上方延伸并具有埋设部分和延伸部分。 至少延伸部分包括具有倒置的“V”带隙轮廓的半导体材料，带隙值从结构的横向边缘处的第一值逐渐增加到高于第一值的第二值，高于第一值 结构。 本公开还涉及制造这种带状工程半导体器件的方法。

公开(公告)号：US20140099774A1

公开(公告)日：2014-04-10

申请号：US14047950

申请日：2013-10-07

Applicant: IMEC

Inventor： Benjamin Vincent

IPC: H01L29/161

CPC classification number: H01L29/161 ,  H01L29/66795

Abstract: Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer.

Abstract translation: 公开了形成翅片的方法。 在一个示例性实施例中，一种方法包括提供包括由隔离区隔开的至少两个细长结构的衬底。 每个细长结构包括第一半导体材料和第二半导体材料的半导体合金，并且细长结构的松弛部分包括处于松弛且基本上无缺陷状态的半导体合金。 该方法还包括使基底经受缩合氧化，使得每个细长结构形成翅片和氧化物层。 翅片包括由半导体合金形成的翅片基部和处于应变状态的第一半导体材料的翅片顶部。 翅片顶部由第一半导体材料的冷凝形成。 氧化物层包括第二半导体材料的氧化物。 该方法还包括去除氧化物层中的至少一些。

公开(公告)号：US20130233238A1

公开(公告)日：2013-09-12

申请号：US13768462

申请日：2013-02-15

Applicant: IMEC

Inventor： Benjamin Vincent ,  Aaron Thean ,  Liesbeth Witters

IPC: C30B23/04 ,  C30B25/04 ,  C30B19/00

CPC classification number: H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.

Abstract translation: 公开了用于外延生长基本上无缺陷的半导体材料的方法和掩模结构。 在一些实施例中，该方法可以包括提供包括第一晶体材料的基底，其中第一晶体材料具有第一晶格常数; 在所述衬底上提供掩模结构，其中所述掩模结构包括第一层，所述第一层包括延伸穿过所述第一层的第一开口（其中所述第一开口的底部包括所述衬底），以及在所述第一层的顶部上的第二层， 第二级包括相对于第一开口非零角度定位的多个第二沟槽。 该方法还可以包括在第一开口的底部上外延生长第二晶体材料，其中第二晶体材料具有不同于第一晶格常数的第二晶格常数，并且第二晶体材料中的缺陷被捕获在第一开口中。

公开(公告)号：US09263528B2

公开(公告)日：2016-02-16

申请号：US14047950

申请日：2013-10-07

Applicant: IMEC

Inventor： Benjamin Vincent

IPC: H01L21/479 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L29/66795

Abstract: Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer.

Abstract translation: 公开了形成翅片的方法。 在一个示例性实施例中，一种方法包括提供包括由隔离区隔开的至少两个细长结构的衬底。 每个细长结构包括第一半导体材料和第二半导体材料的半导体合金，并且细长结构的松弛部分包括处于松弛且基本上无缺陷状态的半导体合金。 该方法还包括使基底经受缩合氧化，使得每个细长结构形成翅片和氧化物层。 翅片包括由半导体合金形成的翅片基部和处于应变状态的第一半导体材料的翅片顶部。 翅片顶部由第一半导体材料的冷凝形成。 该氧化物层包括第二半导体材料的氧化物。 该方法还包括去除氧化物层中的至少一些。

公开(公告)号：US20140151766A1

公开(公告)日：2014-06-05

申请号：US14086486

申请日：2013-11-21

Applicant: IMEC

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract translation: 提供FinFET器件和制造FinFET器件的方法。 示例性装置可以包括包括至少两个翅片结构的基板。 所述至少两个翅片结构中的每一个可以与源极和漏极区域接触，并且所述至少两个鳍结构中的每一个可以包括覆盖并与衬底接触的应变松弛缓冲器（SRB），并且上层覆盖和 与SRB联系。 可以选择上层和SRB的组成，使得第一鳍结构的上层在生长状态下经受第一迁移率增强应变，第一迁移率增强应变沿纵向施加于 源极区到漏极区，并且其中第二鳍结构的上层的至少上部被应变松弛。

公开(公告)号：US10340139B2

公开(公告)日：2019-07-02

申请号：US15333995

申请日：2016-10-25

Applicant: IMEC

Inventor： Benjamin Vincent ,  Voon Yew Thean ,  Liesbeth Witters

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  C30B25/04 ,  C30B23/04 ,  C30B19/12 ,  C30B19/00

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.