公开(公告)号：US20240119998A1

公开(公告)日：2024-04-11

申请号：US18482263

申请日：2023-10-06

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Francky Catthoor ,  Dawit Burusie Abdi

IPC: G11C11/419 ,  G11C5/06 ,  H01L25/065 ,  H10B10/00 ,  H10B80/00

CPC classification number: G11C11/419 ,  G11C5/063 ,  H01L25/0657 ,  H10B10/125 ,  H10B80/00 ,  H01L2225/06506

Abstract: The disclosed 3D IC includes a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit.

公开(公告)号：US11847944B2

公开(公告)日：2023-12-19

申请号：US16972838

申请日：2019-06-03

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Jan Genoe ,  Xavier Rottenberg

IPC: G09G3/00 ,  G09G3/20 ,  G03H1/04

CPC classification number: G09G3/003 ,  G09G3/2085 ,  G03H1/04 ,  G09G3/20 ,  G09G2310/0213 ,  G09G2310/0297

Abstract: A system and for distributing data for 3D light field projection and a method thereof. The system comprises input terminals and output terminals that are connectable to pixel elements of a display. Data paths are established between input terminals and output terminals, and are controlled by data switches. The system also comprises a control plane adapted for applying control variables to the data switches. Control switches of the control plane select the control variables which are applied to the data switches. Sequences of control variables and enable variables propagate along at least one first delay line and along at least one second delay line, respectively. Delay units of the at least one first delay line and of the at least one second delay line have a synchronous relationship. During system run-time patterns contained in the stream of input data are detected for determining the sequences of control variables.

公开(公告)号：US11677401B2

公开(公告)日：2023-06-13

申请号：US17740759

申请日：2022-05-10

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Edouard Giacomin ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H03K19/17736 ,  H01L27/06

CPC classification number: H03K19/17744 ,  H01L27/0688

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising:



a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors,
wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and
wherein each logic cell comprises:

a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and
a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.

公开(公告)号：US20230179315A1

公开(公告)日：2023-06-08

申请号：US18049932

申请日：2022-10-26

Applicant: IMEC VZW ,  ShanghaiTech University

Inventor： Xinzhe Liu ,  Raees Kizhakkumkara Muhamad ,  Dessislava Nikolova ,  Yajun Ha ,  Francky Catthoor ,  Fupeng Chen ,  Peter Schelkens ,  David Blinder

IPC: H04J11/00

CPC classification number: H04J11/00

Abstract: Example embodiments relate to methods for disseminating scaling information and applications thereof in very large scale integration (VLSI) implementations of fixed-point fast Fourier transforms (FFTs). One embodiment includes a method for disseminating scaling information in a system. The system includes a linear decomposable transformation process and an inverse process of the linear decomposable transformation process. The inverse process of the linear decomposable transformation process is defined, in time or space, as an inverse linear decomposable transformation process. The linear decomposable transformation process is separated from the inverse linear decomposable transformation process. The linear decomposable transformation process or the inverse linear decomposable transformation process is able to be performed first and is defined as a linear decomposable transformation I. The other remaining process is performed subsequently and is defined as a linear decomposable transformation II. The method for disseminating scaling information is used for a bit width-optimized and energy-saving hardware implementation.

公开(公告)号：US10592430B2

公开(公告)日：2020-03-17

申请号：US15726749

申请日：2017-10-06

Applicant: IMEC VZW ,  Stichting IMEC Nederland ,  UNIVERSIDAD COMPLUTENSE DE MADRID

Inventor： Francky Catthoor ,  Matthias Hartmann ,  Jose Ignacio Gomez ,  Christian Tenllado ,  Sotiris Xydis ,  Javier Setoain Rodrigo ,  Thomas Papastergiou ,  Christos Baloukas ,  Anup Kumar Das ,  Dimitrios Soudris

IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/122 ,  G06F12/128 ,  G06F12/0864 ,  G06F12/08 ,  G06F12/02

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

公开(公告)号：US20170091094A1

公开(公告)日：2017-03-30

申请号：US15250188

申请日：2016-08-29

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Matthias Hartmann ,  Komalan Manu Perumkunnil ,  Jose Ignacio Gomez ,  Christian Tenllado

IPC: G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/0811 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0685 ,  G06F3/0688 ,  G06F8/41 ,  G06F8/452 ,  G06F9/30036 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/0897 ,  G06F13/1657 ,  G06F13/1673 ,  G06F15/781 ,  G06F15/7846 ,  G06F2212/1016 ,  G06F2212/222 ,  G06F2212/454 ,  G06F2212/601 ,  G06F2212/6028 ,  G11C7/10 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675

Abstract: The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.

公开(公告)号：US20160283629A1

公开(公告)日：2016-09-29

申请号：US15081635

申请日：2016-03-25

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Pieter Weckx ,  Dmitrios Rodopoulos ,  Benjamin Kaczer ,  Francky Catthoor

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/76 ,  G06F2217/80 ,  G06F2217/82

Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

Abstract translation: 公开了一种用于模拟电子电路的系统和方法。 该方法包括创建从n维参数空间内选择的电路或设备参数点的有限集合。 该方法包括针对该组的每个电路或设备参数点确定性能度量的对应响应值和相应的发生概率。 该方法包括针对性能度量的预定值确定总出现概率。

公开(公告)号：US11381242B2

公开(公告)日：2022-07-05

申请号：US17063003

申请日：2020-10-05

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Edouard Giacomin ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H03K19/17736 ,  H01L27/06

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.

公开(公告)号：US20210247720A1

公开(公告)日：2021-08-12

申请号：US16972838

申请日：2019-06-03

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Jan Genoe ,  Xavier Rottenberg

IPC: G03H1/04 ,  G09G3/20

Abstract: A system and for distributing data for 3D light field projection and a method thereof. The system comprises input terminals and output terminals that are connectable to pixel elements of a display. Data paths are established between input terminals and output terminals, and are controlled by data switches. The system also comprises a control plane adapted for applying control variables to the data switches. Control switches of the control plane select the control variables which are applied to the data switches. Sequences of control variables and enable variables propagate along at least one first delay line and along at least one second delay line respectively. Delay units of the at least one first delay line and of the at least one second delay line have a synchronous relationship. During system run-time patterns contained in the stream of input data are detected for determining the sequences of control variables.

公开(公告)号：US20190197203A1

公开(公告)日：2019-06-27

申请号：US16215216

申请日：2018-12-10

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Francky Catthoor ,  Maria-Iro Baka ,  Patrizio Manganiello

IPC: G06F17/50 ,  G01W1/12 ,  H02S50/10

CPC classification number: G06F17/5009 ,  G01W1/12 ,  G05F1/67 ,  G06F2217/16 ,  G06F2217/80 ,  H02J3/385 ,  H02J2003/003 ,  H02J2003/007 ,  H02S50/10

Abstract: A method for generating/updating a database of current-voltage characteristic curves is disclosed. This method includes simulating for at least one combination of a topology of a photovoltaic cell group, an internal cell temperature(s) and a cell irradiation(s), a model of the photovoltaic cell group to provide a representative current-voltage characteristic curve, and clustering the current-voltage characteristic curves to identify at least one plurality of similar current-voltage characteristic curves. The method also includes generating a many-to-one mapping in the database to map query requests corresponding to each of the at least one plurality of similar current-voltage characteristic curves onto a single representative current-voltage characteristic curve for that plurality, each query request identifying a topology of a photovoltaic cell group, at least one internal temperature for the photovoltaic cells in the photovoltaic cell group and at least one cell irradiation for the photovoltaic cells in the photovoltaic cell group.