公开(公告)号：US11677401B2

公开(公告)日：2023-06-13

申请号：US17740759

申请日：2022-05-10

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Edouard Giacomin ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H03K19/17736 ,  H01L27/06

CPC classification number: H03K19/17744 ,  H01L27/0688

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising:



a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors,
wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and
wherein each logic cell comprises:

a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and
a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.

公开(公告)号：US11488826B2

公开(公告)日：2022-11-01

申请号：US16931230

申请日：2020-07-16

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Yong Kong Siew ,  Juergen Boemmels

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.

公开(公告)号：US11244949B2

公开(公告)日：2022-02-08

申请号：US16441725

申请日：2019-06-14

Applicant: IMEC vzw

Inventor： Pieter Weckx ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L29/76 ,  H01L27/11 ,  G11C5/02 ,  G11C5/06 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8238

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

公开(公告)号：US10748815B2

公开(公告)日：2020-08-18

申请号：US16663796

申请日：2019-10-25

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Julien Ryckaert

IPC: H01L21/8234 ,  H01L29/423

Abstract: The present disclosure relates to three dimensional (3D) transistor structures and methods of forming the same. In an aspect, a method comprises providing a vertical stack of alternating layers of channel material and dummy material, forming a first set of fins on the stack, and forming a second fin above the first set of fins, the second fin extending orthogonal to the first set of fins. Further, the first set of fins is cut into a set of fin portions, using the second fin and a first sidewall spacers as an etch mask, and second sidewall spacers are formed on the second fin. These structures are used to form a 3D structure of channel regions and source/drain regions forming transistor structures. Advantageously, the 3D semiconductor structure is manufactured using a relatively low number of mask layers per transistor which decreases manufacturing costs.

公开(公告)号：US20180330988A1

公开(公告)日：2018-11-15

申请号：US15979183

申请日：2018-05-14

Applicant: IMEC VZW

Inventor： Juergen Boemmels

IPC: H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L21/311

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to vertical channel devices and methods of forming the vertical channel devices. According to one aspect, a method of forming a vertical channel device includes forming on a semiconductor substrate a plurality of vertical channel structures. The method additionally includes forming gates, where each of the gates wraps around one of the vertical channel structures. The method additionally includes embedding the gates in a first dielectric layer and exposing top portions of the vertical channel structures. The method additionally includes forming top electrodes on corresponding top portions of the vertical channel structures. The method additionally includes forming sidewall etch barriers on sidewalls of each of the top electrodes. The method additionally includes forming a second dielectric layer covering the first dielectric layer and the top electrodes. The method additionally includes etching a set of vertically extending gate contact holes through the first and second dielectric layers and selectively against the sidewall etch barriers, where each of the gate contact holes exposes one of the gates adjacent to one of the top electrodes. The method further includes filling the set of gate contact holes with a conductive material. A vertical channel device fabricated using the method is also disclosed according another aspect.

公开(公告)号：US11295977B2

公开(公告)日：2022-04-05

申请号：US16844442

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Julien Ryckaert

IPC: H01L21/768 ,  G06F30/392 ,  H01L23/522

Abstract: A method of forming an interconnect structure for a standard cell semiconductor device is disclosed. In one aspect, the method includes forming metal lines along respective routing tracks, wherein forming the metal lines includes depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer; patterning the capping layer and the metal layer to form first and second capped off-center metal lines extending along first and second off-center tracks, respectively; forming spacer lines on sidewalls of the capped off-center metal lines; and embedding the spacer-provided capped off-center metal lines in a second dielectric layer. The method further includes patterning a set of trenches in the second dielectric layer. The set of trenches includes a center trench extending along a center track between the spacer-provided capped off-center lines, and a first and a second edge trench extending along first and second edge tracks, respectively, on mutually opposite outer sides of the spacer-provided capped off-center metal lines. The method further includes forming a center metal line in the center trench, and a first and a second edge metal line in the first and second edge trenches, respectively.

公开(公告)号：US11127627B2

公开(公告)日：2021-09-21

申请号：US16695776

申请日：2019-11-26

Applicant: IMEC VZW

Inventor： Frederic Lazzarino ,  Guillaume Bouche ,  Juergen Boemmels

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/02

Abstract: A method for forming an interconnection structure for a semiconductor device is provided. The method includes: (i) forming a conductive layer on an insulating layer; (ii) forming above the conductive layer a first set of mandrel lines of a first material; (iii) forming a set of spacer lines of a second material different from the first material, wherein the spacer lines of the second material are formed on sidewalls of the first set of mandrel lines; (iv) forming a second set of mandrel lines of a third material different from the first and second materials, wherein the second set of mandrel lines fill gaps between spacer lines of the set of spacer lines; (v) cutting at least a first mandrel line of the second set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the second set of mandrel lines selectively to the set of spacer lines and the first set of mandrel lines, cutting at least a first mandrel line of the first set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the first set of mandrel lines selectively to the set of spacer lines and the second set of mandrel lines; (vi) removing the set of spacer lines, selectively to the first and second sets of mandrel lines, thereby forming an alternating pattern of mandrel lines of the first set of mandrel lines and mandrel lines of the second set of mandrel lines; and (vii) patterning the conductive layer to form a set of conductive lines, wherein the patterning comprises etching while using the alternating pattern of mandrel lines of the first and second sets of mandrel lines as an etch mask.

公开(公告)号：US10833161B2

公开(公告)日：2020-11-10

申请号：US16253321

申请日：2019-01-22

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Julien Ryckaert ,  Juergen Boemmels ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

公开(公告)号：US20200328109A1

公开(公告)日：2020-10-15

申请号：US16844442

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Julien Ryckaert

IPC: H01L21/768 ,  H01L23/522 ,  G06F30/392

Abstract: A method of forming an interconnect structure for a standard cell semiconductor device is disclosed. In one aspect, the method includes forming metal lines along respective routing tracks, wherein forming the metal lines includes depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer; patterning the capping layer and the metal layer to form first and second capped off-center metal lines extending along first and second off-center tracks, respectively; forming spacer lines on sidewalls of the capped off-center metal lines; and embedding the spacer-provided capped off-center metal lines in a second dielectric layer. The method further includes patterning a set of trenches in the second dielectric layer. The set of trenches includes a center trench extending along a center track between the spacer-provided capped off-center lines, and a first and a second edge trench extending along first and second edge tracks, respectively, on mutually opposite outer sides of the spacer-provided capped off-center metal lines. The method further includes forming a center metal line in the center trench, and a first and a second edge metal line in the first and second edge trenches, respectively.

公开(公告)号：US10763159B2

公开(公告)日：2020-09-01

申请号：US16518361

申请日：2019-07-22

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Christopher Wilson ,  Juergen Boemmels

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522

Abstract: A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.