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    CHIP PACKAGE
    2.
    发明申请
    CHIP PACKAGE 有权

    公开(公告)号：US20220310473A1

    公开(公告)日：2022-09-29

    申请号：US17839500

    申请日：2022-06-14

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/495 ,  H01L23/373 ,  H01L23/433

    Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

    Chip package
    3.
    发明授权
    Chip package 有权

    公开(公告)号：US11387159B2

    公开(公告)日：2022-07-12

    申请号：US16808369

    申请日：2020-03-04

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/31 ,  H01L23/433

    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

    Hetero-integrated structure
    4.
    发明授权
    Hetero-integrated structure 有权

    公开(公告)号：US11004816B2

    公开(公告)日：2021-05-11

    申请号：US16553179

    申请日：2019-08-28

    Applicant: Industrial Technology Research Institute

    Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Tao-Chih Chang ,  Wei-Chung Lo

    IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

    CHIP PACKAGE
    5.
    发明申请
    CHIP PACKAGE 审中-公开

    公开(公告)号：US20190109064A1

    公开(公告)日：2019-04-11

    申请号：US15976886

    申请日：2018-05-11

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/495

    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

    SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF 有权
    半导体发光器件及其制造方法

    公开(公告)号：US20160211415A1

    公开(公告)日：2016-07-21

    申请号：US14949893

    申请日：2015-11-24

    Applicant: Industrial Technology Research Institute

    Inventor： Yu-Wei Huang ,  Tao-Chih Chang ,  Chih-Ming Shen

    IPC: H01L33/38 ,  H01L27/15 ,  H01L33/62

    CPC classification number: H01L25/0753 ,  H01L21/4853 ,  H01L21/68 ,  H01L21/6835 ,  H01L24/00 ,  H01L33/0079 ,  H01L33/483 ,  H01L33/62 ,  H01L2221/68363 ,  H01L2933/0066

    Abstract: A semiconductor light emitting device including a substrate, a plurality of semiconductor light emitting units and a plurality of non-conductive walls is provided. The semiconductor light emitting device is disposed on the substrate in an array. Each of the semiconductor light emitting units has a first electrode and a second electrode opposite to the first electrode. Each of the semiconductor light emitting units is electrically connected to the substrate through the first electrode, and the semiconductor light emitting units are electrically connected together to a conducting layer through the second electrodes. The semiconductor light emitting units have different emission colors. The non-conductive walls are disposed between adjacent semiconductor light emitting units, to separate the semiconductor light emitting units. A fabricating method of semiconductor light emitting device is also provided.

    Abstract translation: 提供了包括基板，多个半导体发光单元和多个非导电壁的半导体发光器件。 半导体发光器件以阵列方式设置在衬底上。 每个半导体发光单元具有第一电极和与第一电极相对的第二电极。 每个半导体发光单元通过第一电极电连接到基板，并且半导体发光单元通过第二电极电连接到导电层。 半导体发光单元具有不同的发射颜色。 非导电壁设置在相邻的半导体发光单元之间，以分离半导体发光单元。 还提供了半导体发光器件的制造方法。

    Chip scale package structures
    8.
    发明授权
    Chip scale package structures 有权

    公开(公告)号：US11538842B2

    公开(公告)日：2022-12-27

    申请号：US17019026

    申请日：2020-09-11

    Applicant: Industrial Technology Research Institute

    Inventor： Yu-Min Lin ,  Tao-Chih Chang

    IPC: H01L27/146

    Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.

    Package structure and method for connecting components
    9.
    发明授权
    Package structure and method for connecting components 有权

    公开(公告)号：US11355472B2

    公开(公告)日：2022-06-07

    申请号：US16264689

    申请日：2019-02-01

    Applicant: Industrial Technology Research Institute

    Inventor： Yu-Min Lin ,  Tao-Chih Chang ,  Wei-Chung Lo

    IPC: H01L23/00 ,  H01L27/146

    Abstract: A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

    CHIP PACKAGE STRUCTURE
    10.
    发明申请
    CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210035914A1

    公开(公告)日：2021-02-04

    申请号：US16849999

    申请日：2020-04-16

    Applicant: Industrial Technology Research Institute

    Inventor： Hsin-Han Lin ,  Yu-Min Lin ,  Tao-Chih Chang

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367

    Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

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