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公开(公告)号：US10381919B2
公开(公告)日：2019-08-13
申请号：US15379055
申请日：2016-12-14
Applicant: Infineon Technologies AG
Inventor： Albino Pidutti , Damiano Gadler , Herbert Gietler , Michael Lenz , Yavuz Kilic , Ioannis Pachnis
Abstract: A rectifier is described herein. According to one example, the rectifier includes a semiconductor substrate and further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode that is connected parallel to a load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. Further, the rectifier includes a control circuit that is configured to switch the first MOS transistor on for an on-time period, during which the diode is forward biased. The first MOS transistor, the diode, and the control circuit are integrated in the semiconductor substrate.
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公开(公告)号：US10516343B2
公开(公告)日：2019-12-24
申请号：US15446568
申请日：2017-03-01
Applicant: Infineon Technologies AG
Inventor： Juergen Kositza , Herbert Gietler , Harald Huber , Michael Lenz
Abstract: A power semiconductor package includes a reference voltage terminal, a supply voltage terminal, a phase terminal, a first power transistor and a second power transistor. The first power transistor and the second power transistor are connected in series and form a low side switch and a high side switch of a half bridge circuit.
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公开(公告)号：US20180167000A1
公开(公告)日：2018-06-14
申请号：US15378945
申请日：2016-12-14
Applicant: Infineon Technologies AG
Inventor： Albino Pidutti , Damiano Gadler , Herbert Gietler , Michael Lenz
Abstract: A rectifier device is described herein. In accordance with one example, the rectifier device includes a transistor that has a load current path and a diode connected parallel to the load current path. The diode and the load current path are connected between an anode terminal and a cathode terminal; an alternating input voltage is operably applied between the anode terminal and the cathode terminal. A control circuit is coupled to a gate terminal of the transistor and configured to switch the semiconductor switch on for an on-time period, during which the diode is forward biased. Moreover, a clamping circuit is coupled to a gate terminal of the transistor and configured to at least partly switch on the transistor, while the diode is reverse biased and the level of the alternating input voltage reaches a clamping voltage.
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公开(公告)号：US20160155712A1
公开(公告)日：2016-06-02
申请号：US14555735
申请日：2014-11-28
Applicant: Infineon Technologies AG
Inventor： Herbert Gietler , Robert Pressl
IPC: H01L23/58 , H01L29/06 , G01R31/26 , H01L23/522
CPC classification number: H01L22/34 , G01N27/24 , G01R31/2601 , G01R31/2831 , H01L23/58 , H01L23/642 , H01L29/0649 , H01L29/0684 , H01L2924/0002 , H01L2924/00
Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.
Abstract translation: 根据各种实施例，半导体芯片可以包括：半导体主体区域，包括第一表面和与第一表面相对的第二表面; 用于检测裂纹传播到半导体本体区域中的电容结构; 其中所述电容结构可以包括至少部分地围绕所述半导体本体区域并且至少基本上从所述第一表面延伸到所述第二表面的第一电极区域; 其中所述电容结构还可包括邻近所述第一电极区设置的第二电极区和在所述第一电极区和所述第二电极区之间延伸的电绝缘区。
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公开(公告)号：US20160072376A1
公开(公告)日：2016-03-10
申请号：US14849655
申请日：2015-09-10
Applicant: Infineon Technologies AG
Inventor： Dirk Ahlers , Frank Auer , Herbert Gietler , Michael Lenz
CPC classification number: H02M1/08 , H01L27/0207 , H01L27/0733 , H02K11/046 , H02M7/217 , H02M7/219 , H02M2001/0048 , H02M2007/2195 , Y02B70/1408
Abstract: A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.
Abstract translation: 整流装置包括布置在单个半导体管芯上的功率晶体管，栅极控制电路和电容器结构。 功率晶体管包括连接到整流装置的第一端子的源极或发射极端子，连接到整流装置的第二端子的漏极或集电极端子以及栅极。 栅极控制电路可操作以基于与第一端子和第二端子之间的电压和电流中的至少一个有关的至少一个参数来控制功率晶体管的栅极处的栅极电压。
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Patent Agency Ranking
公开(公告)号：US20140117511A1
公开(公告)日：2014-05-01
申请号：US13664311
申请日：2012-10-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Kurt Matoy , Hubert Maier , Christian Krenn , Elfriede Kraxner Wellenzohn , Helmut Schoenherr , Juergen Steinbrenner , Markus Kahn , Fister Schlemitz Silvana , Christoph Brunner , Herbert Gietler , Uwe Hoeckele
CPC classification number: H01L23/3171 , H01L21/0206 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/02334 , H01L21/0234 , H01L21/76801 , H01L23/291
Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
Abstract translation: 公开了钝化层和制备钝化层的方法。 在一个实施例中，制造钝化层的方法包括在工件上沉积第一硅基电介质层，第一硅基电介质层包含氮，并在第一硅基电介质层上原位沉积第二硅基电介质层， 所述第二电介质层包含氧。
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公开(公告)号：US10291108B2
公开(公告)日：2019-05-14
申请号：US14849655
申请日：2015-09-10
Applicant: Infineon Technologies AG
Inventor： Dirk Ahlers , Frank Auer , Herbert Gietler , Michael Lenz
Abstract: A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.
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公开(公告)号：US20170133289A1
公开(公告)日：2017-05-11
申请号：US15413442
申请日：2017-01-24
Applicant: Infineon Technologies AG
Inventor： Herbert Gietler , Robert Pressl
CPC classification number: H01L22/34 , G01N27/24 , G01R31/2601 , G01R31/2831 , G01R31/2856 , H01L21/78 , H01L23/58 , H01L23/585 , H01L23/642 , H01L29/0649 , H01L29/0684 , H01L2224/291 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2924/0002 , H01L2924/00 , H01L2924/014 , H01L2924/00014
Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.
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公开(公告)号：US20150235917A1
公开(公告)日：2015-08-20
申请号：US14699704
申请日：2015-04-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Kurt Matoy , Hubert Maier , Christian Krenn , Elfriede Kraxner Wellenzohn , Helmut Schoenherr , Juergen Steinbrenner , Markus Kahn , Silvana Fister , Christoph Brunner , Herbert Gietler , Uwe Hoeckele
CPC classification number: H01L23/3171 , H01L21/0206 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/02334 , H01L21/0234 , H01L21/76801 , H01L23/291
Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
Abstract translation: 公开了钝化层和制备钝化层的方法。 在一个实施例中，制造钝化层的方法包括在工件上沉积第一硅基电介质层，第一硅基电介质层包含氮，并在第一硅基电介质层上原位沉积第二硅基电介质层， 所述第二电介质层包含氧。
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公开(公告)号：US20180166971A1
公开(公告)日：2018-06-14
申请号：US15379055
申请日：2016-12-14
Applicant: Infineon Technologies AG
Inventor： Albino Pidutti , Damiano Gadler , Herbert Gietler , Michael Lenz , Yavuz Kilic , Ioannis Pachnis
CPC classification number: H02M1/32 , H01L29/1095 , H01L29/7813 , H02M1/08 , H02M7/217 , H02M7/219
Abstract: A rectifier is described herein. According to one example, the rectifier includes a semiconductor substrate and further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode that is connected parallel to a load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. Further, the rectifier includes a control circuit that is configured to switch the first MOS transistor on for an on-time period, during which the diode is forward biased. The first MOS transistor, the diode, and the control circuit are integrated in the semiconductor substrate.
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