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    NON-ROUGHENED CU TRACE WITH ANCHORING TO REDUCE INSERTION LOSS OF HIGH SPEED IO ROUTING IN PACKAGE SUBSTRATE
    2.
    发明申请
    NON-ROUGHENED CU TRACE WITH ANCHORING TO REDUCE INSERTION LOSS OF HIGH SPEED IO ROUTING IN PACKAGE SUBSTRATE 审中-公开

    公开(公告)号：US20190295937A1

    公开(公告)日：2019-09-26

    申请号：US15927047

    申请日：2018-03-20

    Applicant: Intel Corporation

    Inventor： Chong ZHANG ,  Ying WANG ,  Cheng XU ,  Hongxia FENG ,  Meizi JIAO ,  Junnan ZHAO ,  Yikang DENG

    IPC: H01L23/498 ,  C23C18/26 ,  H05K1/11 ,  H01L23/00 ,  H01L21/48

    Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a trace disposed on a conductive layer. The semiconductor package has one or more adhesion anchoring points and a plurality of portions on the trace. An adhesion anchoring point is between two portions on the trace. A surface roughness of an adhesion anchoring point is greater than a surface roughness of a portion on the trace. The trace may be a high-speed input/output (HSIO) trace. The semiconductor package may include via pads disposed on each end of the trace, and a dielectric disposed on the trace. The dielectric is patterned to form openings on the dielectric that expose second portions on the trace. The dielectric remains over the portions. The semiconductor package may have a chemical treatment disposed on the exposed openings on the trace to form the adhesion anchoring points.

    DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING
    4.
    发明申请
    DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING 审中-公开

    公开(公告)号：US20190393143A1

    公开(公告)日：2019-12-26

    申请号：US16017671

    申请日：2018-06-25

    Applicant: Intel Corporation

    Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

    IPC: H01L23/498 ,  H01L21/48

    Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

    CORE LAYER WITH FULLY ENCAPSULATED CO-AXIAL MAGNETIC MATERIAL AROUND PTH IN IC PACKAGE SUBSTRATE
    10.
    发明申请
    CORE LAYER WITH FULLY ENCAPSULATED CO-AXIAL MAGNETIC MATERIAL AROUND PTH IN IC PACKAGE SUBSTRATE 审中-公开

    公开(公告)号：US20190274217A1

    公开(公告)日：2019-09-05

    申请号：US15910288

    申请日：2018-03-02

    Applicant: Intel Corporation

    Inventor： Chong ZHANG ,  Ying WANG ,  Junnan ZHAO ,  Cheng XU ,  Yikang DENG

    IPC: H05K1/16 ,  H01F27/28 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04

    Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

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