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公开(公告)号：US20220284968A1
公开(公告)日：2022-09-08
申请号：US17825960
申请日：2022-05-26
Applicant: Intel Corporation
Inventor： Wei Cao , Richard M. Fastow , Xuehong Yu , Xin Sun , Hyungseok Kim , Narayanan Ramanan , Amol R. Joshi , Krishna Parat
Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
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Patent Agency Ranking
公开(公告)号：US20220028459A1
公开(公告)日：2022-01-27
申请号：US16947219
申请日：2020-07-23
Applicant: Intel Corporation
Inventor： Wei Cao , Richard M. Fastow , Xuehong Yu , Xin Sun , Hyungseok Kim , Narayanan Ramanan , Amol R. Joshi , Krishna Parat
Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
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公开(公告)号：US20230154539A1
公开(公告)日：2023-05-18
申请号：US17528892
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Shantanu R. Rajwade , Christian Mion , Pranav Kalavade , Rohit S. Shenoy , Xin Sun , Kristopher Gaewsky
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3459 , G06F3/061 , G06F3/0659 , G06F3/0679 , G11C11/56
Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.
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公开(公告)号：US10325665B2
公开(公告)日：2019-06-18
申请号：US15836124
申请日：2017-12-08
Applicant: INTEL CORPORATION
Inventor： Richard Fastow , Xin Sun , Uday Chandrasekhar , Krishna K. Parat , Camila Jaramillo , Purval S. Sule , Aliasgar S. Madraswala
Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.
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公开(公告)号：US11355199B2
公开(公告)日：2022-06-07
申请号：US16947219
申请日：2020-07-23
Applicant: Intel Corporation
Inventor： Wei Cao , Richard M. Fastow , Xuehong Yu , Xin Sun , Hyungseok Kim , Narayanan Ramanan , Amol R. Joshi , Krishna Parat
Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
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公开(公告)号：US12243590B2
公开(公告)日：2025-03-04
申请号：US17528892
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Shantanu R. Rajwade , Christian Mion , Pranav Kalavade , Rohit S. Shenoy , Xin Sun , Kristopher Gaewsky
Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.
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