公开(公告)号：US12289896B2

公开(公告)日：2025-04-29

申请号：US17644449

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Oscar van der Straten ,  Willie Lester Muchrison, Jr. ,  Lisamarie White ,  Chih-Chao Yang

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A magneto-resistive random access memory with segmented bottom electrode includes a magnetic tunnel junction pillar above a first portion of a bottom electrode layer, the first portion of the bottom electrode layer includes a metal region. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar and above a second portion of the bottom electrode layer including a metal-oxide region. The first portion of the bottom electrode layer composed of the metal region and the second portion of the bottom electrode layer composed of the metal-oxide region form the segmented bottom electrode.

公开(公告)号：US20250120324A1

公开(公告)日：2025-04-10

申请号：US18483864

申请日：2023-10-10

Applicant: International Business Machines Corporation

Inventor： Oscar van der Straten ,  Chih-Chao Yang ,  Ashim Dutta ,  Wu-Chang Tsai ,  Ailian Zhao ,  Pei-I Wang ,  Shravana Kumar Katakam

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode and a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. A top electrode is disposed on the MTJ. The top electrode includes two or more tiers wherein each tier successively includes a smaller footprint.

公开(公告)号：US20250107452A1

公开(公告)日：2025-03-27

申请号：US18472289

申请日：2023-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oscar van der Straten ,  Chih-Chao Yang ,  Koichi Motoyama

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack. A semiconductor device is provided. The semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack, where the tunneling barrier comprises a center portion and two outer portions, where the center portion is on an upper horizontal portion of the reference layer, and the two outer portions are on a slanted upper surface of an encapsulation layer surrounding the reference layer. Forming a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack.

公开(公告)号：US20250062225A1

公开(公告)日：2025-02-20

申请号：US18451870

申请日：2023-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Ailian Zhao ,  Wu-Chang Tsai

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532 ,  H01L23/62 ,  H01L21/768

Abstract: A fuse structure including a first conductive line and a second conductive line, a first metal pillar extending vertically from a top surface of the first conductive line and a second metal pillar extending vertically from a top surface of the second conductive line, a conductive link electrically connecting a top surface of the first metal pillar with a top surface of the second metal pillar, where both the first conductive line and the second conductive line are a different material than both the first metal pillar and the second metal pillar, and where both the first metal pillar and the second metal pillar are a different metal than the conductive link.

公开(公告)号：US20250029917A1

公开(公告)日：2025-01-23

申请号：US18356386

申请日：2023-07-21

Applicant: International Business Machines Corporation

Inventor： Huimei Zhou ,  Lili Cheng ,  Baozhen Li ,  Chih-Chao Yang ,  Miaomiao Wang

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a metal-insulator-metal capacitor disposed between a first metallization level and a second metallization level, the metal-insulator-metal capacitor comprising a first electrode, a second electrode and a third electrode. A first via is extended from and contacts a conductive line of the second metallization level, and a second via is extended from and contacts the first via. The second via contacts the first electrode and the third electrode of the metal-insulator-metal capacitor. A slope of a side surface of the first via is different from a slope of a side surface of the second via.

公开(公告)号：US20240429270A1

公开(公告)日：2024-12-26

申请号：US18340052

申请日：2023-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： HUIMEI ZHOU ,  Shahrukh Khan ,  Baozhen Li ,  Ruilong Xie ,  Yoo-Mi Lee ,  Chih-Chao Yang

IPC: H01G4/005 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A metal insulator metal capacitor (MIM capacitor) between adjacent stacked nanosheet FETs, each include a first nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another and a second nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the second nanosheet stack on the first nanosheet stack. Forming adjacent stacked nanosheet FETs, each include a first nanosheet stack and a second nanosheet stack, the second nanosheet stack on the first nanosheet stack, and forming a MIM capacitor between adjacent stacked nanosheet field effect transistors.

公开(公告)号：US20240421064A1

公开(公告)日：2024-12-19

申请号：US18334430

申请日：2023-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chanro Park ,  Ruilong Xie ,  Julien Frougier ,  Chih-Chao Yang ,  Ashim Dutta ,  Shravana Kumar Katakam

IPC: H01L23/522

Abstract: A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry, where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. A semiconductor device including a metal insulator metal capacitor (MIM capacitor), where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. Forming back end of line Mx-1 metal line layer, forming a plurality of Vx-1 via on the Mx-1 metal line layer, forming Mx metal line layer with subtractive patterning on the plurality of the Vx-1 via, forming a plurality of Vx via on the Mx metal line layer with subtractive patterning; and forming a block mask protecting a portion of the semiconductor device.

公开(公告)号：US20240304546A1

公开(公告)日：2024-09-12

申请号：US18179417

申请日：2023-03-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oscar van der Straten ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53266

Abstract: A structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a first region and a second region one above another, where the first region comprises a width which increases relative to height, and where the second region comprises a width which decreases relative to height.

公开(公告)号：US12087624B2

公开(公告)日：2024-09-10

申请号：US17481198

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Koichi Motoyama ,  Kenneth Chun Kuen Cheng ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/53238

Abstract: A dielectric layer is located on top of and in contact with a substrate. A conductive line located within the dialectic layer. A barrier layer on top of an in contact with the dielectric layer. The barrier layer is below the conductive line. A liner layer on top of and in contact with the barrier layer and below and in contact with the conductive line. A metal liner on top of and in contact with the conductive line. A capping layer on top of and in contact with the dielectric layer, the barrier layer, the liner layer, and the metal liner.

公开(公告)号：US20240266409A1

公开(公告)日：2024-08-08

申请号：US18164651

申请日：2023-02-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tsung-Sheng Kang ,  Curtis S. Durfee ,  Ruqiang Bao ,  Chih-Chao Yang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/4175 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Embodiments of present invention provide a method of forming backside source/drain contact. The method includes forming a dummy contact structure in a substrate, the dummy contact structure having a central portion and a side portion, the central portion being higher than the side portion to have a height above the substrate; forming a source/drain region of a first transistor and a second transistor above the dummy contact structure, the first and second transistors being above the substrate; removing the dummy contact structure from a backside of the substrate to create a backside contact opening; and forming a backside source/drain contact by filling the backside contact opening with a conductive material. Structure of the backside source/drain contact formed thereby is also provided.