公开(公告)号：US20230095749A1

公开(公告)日：2023-03-30

申请号：US17947353

申请日：2022-09-19

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Alexander Roth ,  Catharina Wille

IPC: H01L23/00 ,  B23K35/02 ,  B23K35/26

Abstract: A solder material is provided. The solder material may include a first amount of particles having particle sizes forming a first size distribution, a second amount of particles having particle sizes forming a second size distribution, the particle sizes of the second size distribution being larger than the particle sizes of the first size distribution, and a solder base material in which the first amount of particles and the second amount of particles is distributed. The first amount of particles and the second amount of particles consist of or essentially consist of a metal of a first group of metals. The first group of metals includes copper, silver, gold, palladium, platinum, iron, cobalt, and aluminum. The solder base material includes a metal of a second group of metals. The second group of metals includes tin, indium, zinc, gallium, germanium, antimony, and bismuth.

公开(公告)号：US20200381314A1

公开(公告)日：2020-12-03

申请号：US16884756

申请日：2020-05-27

Applicant: Infineon Technologies AG

Inventor： Wu Hu Li ,  Stefan Schwab ,  Verena Muhr ,  Edmund Riedl ,  Alexander Roth ,  Harry Sax

IPC: H01L21/66 ,  H01L21/48 ,  B05D1/02 ,  C25D3/22 ,  C25D5/18 ,  C25D7/12

Abstract: A method for providing coated leadframes in a process line includes: feeding a plurality of leadframes successively into a process line; depositing a layer onto a main face of the leadframes; measuring physical properties of the layer by one of ellipsometry or reflectometry; assigning measured physical data to any one of a plurality of categories; and depending on a resulting category of the measured physical data, altering process parameters of the depositing, not altering the process parameters of the depositing, or shutting down the process line.

公开(公告)号：US20200266122A1

公开(公告)日：2020-08-20

申请号：US16795234

申请日：2020-02-19

Applicant: Infineon Technologies AG

Inventor： Alexander Roth

IPC: H01L23/373 ,  H01L21/48

Abstract: An electronic component includes a carrier and an electronic chip mounted with compressive strain on the carrier. At least a part of a material of the carrier fulfils at least two of the following three criteria: an offset yield point in a range between 100° C. and 300° C. is at least 300 N/mm2; a yield strength in a range between 100° C. and 300° C. is at least 250 N/mm2; an electrical conductivity at 20° C. is at least 65% of the International Annealed Copper Standard (IACS).

公开(公告)号：US20200231800A1

公开(公告)日：2020-07-23

申请号：US16749425

申请日：2020-01-22

Applicant: Infineon Technologies AG

Inventor： Alexander Roth ,  Edmund Riedl ,  Stefan Schwab

IPC: C08L63/00 ,  H01L23/29 ,  C08G59/68

Abstract: A mold compound includes the following constituents: a matrix composed of a polymer resin, less than 0.1 weight percent of a free adhesion promoter, based on the total weight of the mold compound, for promoting adhesion of the mold compound, a curing agent for curing the polymer resin, and a catalyst for catalysing formation of the mold compound; and a filler.

公开(公告)号：US20180061666A1

公开(公告)日：2018-03-01

申请号：US15688307

申请日：2017-08-28

Applicant: Infineon Technologies AG

Inventor： Alexander Roth

IPC: H01L21/48 ,  H01L23/373 ,  C04B41/00 ,  C04B41/51 ,  C04B41/88 ,  H01L23/498 ,  H01L23/15

Abstract: A method for producing a metal-ceramic substrate with at least one electrically conductive via, in which one metal layer, respectively, is attached in a planar manner to a ceramic plate or a ceramic layer to each of two opposing surface sides of the ceramic layer is provided. The method includes introducing a metal-containing, powdery and/or liquid substance into a hole in the ceramic layer delimiting the via prior to the attachment of both metal layers, or subsequent to the attachment of one of the two metal layers to form an assembly. Prior to the attachment of the other one of the two metal layers, and the assembly is subjected to a high-temperature step above 500° C. in which the metal-containing substance wets the ceramic layer at least partially with a wetting angle of less than 90°.

公开(公告)号：US20240373548A1

公开(公告)日：2024-11-07

申请号：US18772137

申请日：2024-07-13

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Alexander Roth

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/34

Abstract: A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

公开(公告)号：US20240335912A1

公开(公告)日：2024-10-10

申请号：US18750260

申请日：2024-06-21

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Alexander Roth ,  Catharina Wille

IPC: B23K35/02 ,  B22F1/052 ,  B23K35/30 ,  B23K101/40 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: B23K35/0244 ,  B22F1/052 ,  B23K35/0227 ,  B23K35/3033 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49582 ,  H01L24/27 ,  H01L24/29 ,  B22F2301/15 ,  B22F2304/10 ,  B23K2101/40 ,  H01L2224/2746 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29169

Abstract: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin. Methods of forming the layer structure, a chip package and a chip arrangement are also described.

公开(公告)号：US12069802B2

公开(公告)日：2024-08-20

申请号：US16987790

申请日：2020-08-07

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Alexander Roth

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/34

CPC classification number: H05K1/0296 ,  H05K1/09 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/3478

Abstract: A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

公开(公告)号：US11804383B2

公开(公告)日：2023-10-31

申请号：US18075559

申请日：2022-12-06

Applicant: Infineon Technologies AG

Inventor： Alexander Roth

IPC: H01L21/48 ,  C04B35/645 ,  C04B37/02 ,  H05K3/40 ,  C04B41/00 ,  C04B41/51 ,  C04B41/88 ,  H01L23/15 ,  H01L23/373 ,  H01L23/498 ,  H05K1/03 ,  H05K3/02

CPC classification number: H01L21/486 ,  C04B35/6455 ,  C04B37/021 ,  C04B37/026 ,  C04B41/009 ,  C04B41/5127 ,  C04B41/88 ,  H01L21/4807 ,  H01L21/4882 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/49866 ,  H05K3/4061 ,  C04B2235/606 ,  C04B2237/121 ,  C04B2237/124 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/407 ,  C04B2237/62 ,  H05K1/0306 ,  H05K3/022

Abstract: A method for producing a metal-ceramic substrate with a plurality of electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into a plurality of holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the plurality of holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.

公开(公告)号：US20230126663A1

公开(公告)日：2023-04-27

申请号：US18088238

申请日：2022-12-23

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Alexander Roth ,  Catharina Wille

IPC: H01L23/00 ,  B23K35/30 ,  B23K35/02 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  B22F1/052

Abstract: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin.