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    METHOD FOR FORMING A POWER SEMICONDUCTOR MODULE ARRANGEMENT
    2.
    发明公开
    METHOD FOR FORMING A POWER SEMICONDUCTOR MODULE ARRANGEMENT 审中-公开

    公开(公告)号：US20240162048A1

    公开(公告)日：2024-05-16

    申请号：US18505558

    申请日：2023-11-09

    Applicant: Infineon Technologies AG

    Inventor： Lukas Meis ,  Guido Strotmann ,  Florian Dreps

    IPC: H01L21/48 ,  H01L23/498

    CPC classification number: H01L21/4846 ,  H01L23/49811 ,  H01L25/072

    Abstract: A method includes exerting a pressing force on a section of a first surface of a metal layer by a punch. Either the metal layer is arranged on a working surface with a second surface of the metal layer facing the working surface, the second surface being arranged opposite the first surface, and the punch is pressed against the section of the first surface with a pressing force that forces material of the metal layer to flow up against a stroke of the punch, thereby forming a sleeve extending from the first surface in a vertical direction and away from the second surface, or the punch is pressed against the section of the first surface and forced through the metal layer towards the second surface with a pressing force that forces material of the metal layer to flow down with a stroke of the punch, thereby forming a sleeve extending from the second surface in a vertical direction and away from the first surface. The method further includes, after forming the sleeve, arranging the metal layer in a housing of a power semiconductor module.

    Method for Bonding an Electrically Conductive Element to a Bonding Partner
    4.
    发明申请
    Method for Bonding an Electrically Conductive Element to a Bonding Partner 审中-公开

    公开(公告)号：US20190356098A1

    公开(公告)日：2019-11-21

    申请号：US16411950

    申请日：2019-05-14

    Applicant: Infineon Technologies AG

    Inventor： Florian Eacock ,  Guido Strotmann ,  Alparslan Takkac

    IPC: H01R43/02 ,  H01L23/00 ,  H05K3/32 ,  B23K20/10

    Abstract: One aspect relates to a method that includes bonding an electrically conductive element to a bonding surface of a bonding partner by increasing a temperature of a bonding section of the electrically conductive element from an initial temperature to an increased temperature by passing an electric heating current through the bonding section, and pressing the bonding section with a pressing force against the bonding surface using a sonotrode and introducing an ultrasonic vibration into the bonding section via the sonotrode such that the increased temperature of the bonding section, the ultrasonic signal in the bonding section and the pressing force are simultaneously present and cause the formation of a tight and direct bond between the bonding section and the bonding surface.

    METHOD FOR PRODUCING A CIRCUIT CARRIER AND FOR CONNECTING AN ELECTRICAL CONDUCTOR TO A METALLIZATION LAYER OF A CIRCUIT CARRIER
    7.
    发明申请
    METHOD FOR PRODUCING A CIRCUIT CARRIER AND FOR CONNECTING AN ELECTRICAL CONDUCTOR TO A METALLIZATION LAYER OF A CIRCUIT CARRIER 审中-公开
    用于制造电路载体并将电导体连接到电路载体的金属化层的方法

    公开(公告)号：US20160001393A1

    公开(公告)日：2016-01-07

    申请号：US14751361

    申请日：2015-06-26

    Applicant: Infineon Technologies AG

    Inventor： Mark Essert ,  Marianna Nomann ,  Thomas Nuebel ,  Guido Strotmann

    IPC: B23K20/10 ,  B23K20/22

    CPC classification number: B23K20/10 ,  B23K20/22 ,  B23K2101/38 ,  H05K1/0263 ,  H05K1/0306 ,  H05K3/328 ,  H05K2203/0285

    Abstract: One aspect of the invention relates to a method for producing a circuit carrier. For this purpose, an electrically insulating carrier is provided, having an upper side and also an underside opposite from the upper side. A first metal foil and a hardening material are likewise provided. Then, an upper metallization layer, which is arranged on the upper side and has a hardening area, is produced. In this case, at least one contiguous portion of the hardening area is created by at least part of the hardening material being diffused into the first metal foil.

    Abstract translation: 本发明的一个方面涉及一种用于制造电路载体的方法。 为此，提供了一种电绝缘载体，其具有上侧以及与上侧相对的下侧。 同样提供第一金属箔和硬化材料。 然后，制造布置在上侧并具有硬化区域的上金属化层。 在这种情况下，硬化区域的至少一个连续部分由至少部分硬化材料扩散到第一金属箔中而产生。

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