-
公开(公告)号：US20190058448A1
公开(公告)日：2019-02-21
申请号：US16106796
申请日：2018-08-21
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Pantelis Sarais , Peter Singerl , Herwig Wappis
Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.
-
公开(公告)号：US10171039B2
公开(公告)日：2019-01-01
申请号：US14840963
申请日：2015-08-31
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Christian Schuberth , Peter Singerl , Tim Canning , Richard Wilson , Haedong Jang
Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.
-
3.发明申请公开(公告)号：US20170063308A1
公开(公告)日：2017-03-02
申请号：US14840963
申请日：2015-08-31
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Christian Schuberth , Peter Singerl , Tim Canning , Richard Wilson , Haedong Jang
CPC classification number: H03F1/0277 , H03F1/0288 , H03F1/56 , H03F3/193 , H03F3/211 , H03F3/72 , H03F2200/318 , H03F2200/451 , H03F2203/7233
Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.
Abstract translation: 公开了一种峰值放大器。 峰值放大器包括驱动级，最后级和级间匹配网络。 驱动器级具有负载阻抗，并且被配置为基于输入信号产生驱动器输出。 最终阶段具有最终级输入阻抗，并且被配置为基于驱动器输出生成峰值输出。 阶段匹配网络耦合到驱动阶段和最后阶段。 阶段匹配网络被配置为当峰化放大器导通时将最终级输入阻抗转换为驱动级的负载阻抗，并且当峰化放大器处于关闭状态时，将最终级输入阻抗转换为最终级的输入。
-
公开(公告)号：US10958224B2
公开(公告)日：2021-03-23
申请号：US16903011
申请日：2020-06-16
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Pantelis Sarais , Peter Singerl , Herwig Wappis
IPC: H04B1/00 , H03F3/24 , H03F1/02 , H04B1/401 , H03F3/193 , H03F3/19 , H03F3/45 , H04B1/38 , H04J3/02
Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.
-
公开(公告)号：US20180367104A1
公开(公告)日：2018-12-20
申请号：US15627880
申请日：2017-06-20
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Christian Schuberth , Peter Singerl , Ji Zhao
IPC: H03H7/38 , H03F1/56 , H03F1/02 , H03F3/195 , H01L23/66 , H01L29/78 , H01L29/20 , H01L29/778 , H01L23/00 , H01L25/07
Abstract: A circuit includes a first power transistor stage internally configured to function as a voltage-controlled current source, a second power transistor stage having an input impedance which varies as a function of input power and an interstage matching network coupling an output of the first power transistor stage to an input of the second power transistor stage. The interstage matching network is configured to provide impedance inversion between the input of the second power transistor stage and the output of the first power transistor stage. The impedance inversion provided by the interstage matching network transforms the first power transistor stage from functioning as a voltage-controlled current source to functioning as a voltage-controlled voltage source at the input of the second power transistor stage.
-
Patent Agency Ranking
公开(公告)号：US10038404B1
公开(公告)日：2018-07-31
申请号：US15630242
申请日：2017-06-22
Applicant: Infineon Technologies AG
Inventor： Pantelis Sarais , David Seebacher , Peter Singerl , Herwig Wappis
CPC classification number: H03F1/0205 , H03F1/0266 , H03F1/0272 , H03F1/301 , H03F1/304 , H03F3/193 , H03F3/21 , H03F2200/375 , H03F2200/447 , H03F2200/451 , H03F2200/462 , H03F2200/468
Abstract: Techniques are provided for adapting a bias provided to a radio frequency (RF) power amplifier (PA), so as to achieve linear operation over a wide range of conditions. The techniques use open-loop temperature compensation based upon a sensed current during periods when the RF PA is active and inactive. A closed-loop control technique is enabled when the RF PA is inactive. The combined control techniques compensate for temperature variation as well as long-term drift of the semiconductor properties of the devices within the RF PA.
-
公开(公告)号：US20170134194A1
公开(公告)日：2017-05-11
申请号：US14937040
申请日：2015-11-10
Applicant: Infineon Technologies AG
Inventor： Yannis Papananos , David Seebacher , Nikolaos Alexiou , Franz Dielacher , Konstantinos Galanopoulos , Peter Singerl , Marc Tiebout
IPC: H04L25/49
CPC classification number: H04L25/4902 , H04L27/18
Abstract: A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.
-
公开(公告)号：US20160329935A1
公开(公告)日：2016-11-10
申请号：US14704294
申请日：2015-05-05
Applicant: Infineon Technologies AG
Inventor： Peter Singerl , David Seebacher , Thomas Magesacher , Franz Dielacher
CPC classification number: H04L27/205 , H04B1/0475 , H04B1/0483 , H04L25/4902
Abstract: The present disclosure relates to a low-complexity transmitter architecture that drives phase modulators with digital signals to generate a pulse width modulated (PWM) signal that is transmitted by an antenna. In some embodiments, the system has a pre-processing element that generates first and second digital control signals from a digital baseband signal. A first phase modulation component introduces a first phase shift into a first local oscillator signal based upon the first control signal and generates a first digital signal corresponding to the first phase shift. A second phase modulation component introduces a second phase shift into the first local oscillator signal based upon the second control signal and generates a second digital signal corresponding to the second phase shift. A combination element is configured to combine the first and second digital output signals to generate an RF pulse width modulated (RF-PWM) signal.
Abstract translation: 本公开涉及一种低复杂度的发射机架构，其用数字信号驱动相位调制器以产生由天线发射的脉宽调制（PWM）信号。 在一些实施例中，系统具有从数字基带信号产生第一和第二数字控制信号的预处理元件。 第一相位调制分量基于第一控制信号将第一相移引入第一本地振荡器信号，并产生对应于第一相移的第一数字信号。 第二相位调制分量基于第二控制信号将第二相移引入第一本地振荡器信号，并产生对应于第二相移的第二数字信号。 组合元件被配置为组合第一和第二数字输出信号以产生RF脉冲宽度调制（RF-PWM）信号。
-
公开(公告)号：US20140132363A1
公开(公告)日：2014-05-15
申请号：US14159252
申请日：2014-01-20
Applicant: Infineon Technologies AG
Inventor： Peter Singerl , Christian Vogel
IPC: H03K7/08
CPC classification number: H03K7/08 , H03F3/187 , H03F3/217 , H03F2200/351
Abstract: In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.
Abstract translation: 在一个实施例中，从输入信号产生脉冲宽度调制信号的方法包括：基于输入信号计算第一脉冲宽度调制信号的有限数量的基函数，以及基于所计算的有限值形成电子输出 基础功能数量。
-
公开(公告)号：US10930990B2
公开(公告)日：2021-02-23
申请号：US16277398
申请日：2019-02-15
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Andrea Del Chiaro , Christian Schuberth , Peter Singerl , Ji Zhao
Abstract: A device includes at least one electrically conductive structure and at least one stripline. The stripline includes stripline sections that are connected to one another in a series connection between a first terminal and a second terminal. A first subset of the stripline sections is arranged on a first side of the conductive structure and a second subset of the stripline sections is arranged on a second side of the conductive structure. The device also includes at least one conductive connection between the first subset of the stripline sections and the second subset of the stripline sections, wherein the at least one conductive connection is isolated from the at least one electrically conductive structure.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.014 seconds)
