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公开(公告)号：US11144479B2
公开(公告)日：2021-10-12
申请号：US16686379
申请日：2019-11-18
Applicant: Intel Corporation
Inventor： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
IPC: G06F12/00 , G06F12/14 , G06F12/1009 , G06F12/1027 , G06F9/455 , G06F21/78
Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
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公开(公告)号：US11048588B2
公开(公告)日：2021-06-29
申请号：US16787333
申请日：2020-02-11
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Andrew V. Anderson , Richard A. Uhlig , David M. Durham , Ronak Singhal , Xiangbin Wu , Sailesh Kottapalli
Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.
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公开(公告)号：US10599455B2
公开(公告)日：2020-03-24
申请号：US15978501
申请日：2018-05-14
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a hardware processor including event circuit to recognize a virtualization event, and evaluation circuit to determine whether to transfer control of the apparatus from a child guest to a parent guest in response to the virtualization event, wherein the child guest and the parent guest each include a bit per virtualization event to indicate whether the parent guest is to gain control when the virtualization event occurs.
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公开(公告)号：US09747208B2
公开(公告)日：2017-08-29
申请号：US15411658
申请日：2017-01-20
Applicant: Intel Corporation
Inventor： Sanjay Kumar , Rajesh M. Sankaran , Subramanya R. Dulloor , Andrew V. Anderson
IPC: G06F13/00 , G06F12/0804 , G06F11/14
CPC classification number: G06F12/0804 , G06F9/467 , G06F11/07 , G06F11/073 , G06F11/0778 , G06F11/0793 , G06F11/14 , G06F11/1482 , G06F12/0868 , G06F2201/805 , G06F2201/82 , G06F2212/1032 , G06F2212/608
Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
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公开(公告)号：US20170220466A1
公开(公告)日：2017-08-03
申请号：US15011501
申请日：2016-01-30
Applicant: Intel Corporation
Inventor： Deepak K. Gupta , Baiju V. Patel , Andrew V. Anderson , Gilbert Neiger , Ravi L. Sahita
CPC classification number: G06F12/084 , G06F12/1009 , G06F12/1027 , G06F12/109 , G06F2212/1016 , G06F2212/152 , G06F2212/62 , G06F2212/656
Abstract: Embodiments of an invention for sharing a guest physical address space between virtualized contexts are disclosed. In an embodiment, a processor includes a cache memory and a memory management unit. The cache memory includes a plurality of entry locations, each entry location having a guest physical address field and a host physical address field. The memory management unit includes page-walk hardware and cache memory access hardware. The page-walk hardware is to translate a guest physical address to a host physical address using a plurality of page table entries. The cache memory access hardware is to store the guest physical address and the host physical address in the cache memory only if a shareability indicator in at least one of the page table entries is set.
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Patent Agency Ranking
公开(公告)号：US09262338B1
公开(公告)日：2016-02-16
申请号：US14675292
申请日：2015-03-31
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A. Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US09235434B2
公开(公告)日：2016-01-12
申请号：US13837526
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
CPC classification number: G06F9/45533 , G06F9/3861 , G06F9/45545 , G06F9/4555 , G06F9/45558 , G06F9/4812 , G06F9/542 , G06F13/24 , G06F2009/45566
Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
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公开(公告)号：US08949571B2
公开(公告)日：2015-02-03
申请号：US14070561
申请日：2013-11-03
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US12253958B2
公开(公告)日：2025-03-18
申请号：US17496327
申请日：2021-10-07
Applicant: Intel Corporation
Inventor： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
IPC: G06F12/00 , G06F9/455 , G06F12/1009 , G06F12/1027 , G06F12/14 , G06F21/78
Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
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公开(公告)号：US11436161B2
公开(公告)日：2022-09-06
申请号：US16686379
申请日：2019-11-18
Applicant: Intel Corporation
Inventor： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
IPC: G06F12/00 , G06F12/14 , G06F9/455 , G06F12/1009 , G06F12/1027 , G06F21/78
Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
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