公开(公告)号：US20200013533A1

公开(公告)日：2020-01-09

申请号：US16026401

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Malavarayan SANKARASUBRAMANIAN ,  Anne AUGUSTINE ,  Yongki MIN ,  Kaladhar RADHAKRISHNAN

IPC: H01F17/04 ,  H01L23/00 ,  H01F27/28

Abstract: A microelectronics package, comprising a substrate that comprises a dielectric and an inductor component comprising one or more wires within a magnetic core over the dielectric. The inductor component is bonded to the substrate by one or more solder joints. A solder mask is between the inductor component and the dielectric. The one or more solder joints are surrounded by the solder mask, and wherein the solder mask comprises a magnetic material.

公开(公告)号：US20200005983A1

公开(公告)日：2020-01-02

申请号：US16024718

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Malavarayan SANKARASUBRAMANIAN ,  Yongki MIN ,  Anne AUGUSTINE ,  Kaladhar RADHAKRISHNAN ,  Taylor GAINES ,  Ziyin LIN

IPC: H01F27/02 ,  H01F1/42 ,  H01F41/00 ,  H01F1/01 ,  H01L25/16 ,  H01L21/48 ,  H01F27/29

Abstract: Embodiments herein relate to a magnetic encapsulant composite, comprising a mixture of a first material that is a soft magnetic filler, a second material that is a polymer matrix, and a third material that is a process ingredient. The magnetic encapsulant composite may then encapsulate or partially encapsulate a magnetic inductor coupled to a substrate to increase the inductance of the magnetic inductor and/or to strengthen the substrate to which the magnetic inductor and the composite are coupled.

公开(公告)号：US20230319997A1

公开(公告)日：2023-10-05

申请号：US17710944

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Aslam HASWAREY ,  Anne AUGUSTINE ,  Yan Fen SHEN

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/0094 ,  H05K2201/09636 ,  H05K2201/0959 ,  H05K2201/09563 ,  H05K1/181

Abstract: Embodiments herein relate to systems, apparatuses, or processes to using vias, or plated through holes (PTH), within a substrate or within a sub laminate to create capacitors. The interior of a via may have a first layer, or coating, of an electrically conductive material such as copper, formed on the sides of the via. A second layer including a dielectric material is placed on the first layer of the electrically conductive material. A third layer of electrically conductive material may then be placed on the second layer of the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20220093536A1

公开(公告)日：2022-03-24

申请号：US17030121

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  William J. LAMBERT ,  Haifa HARIRI ,  Siddharth KULASEKARAN ,  Mathew MANUSHAROW ,  Anne AUGUSTINE

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48

Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.