公开(公告)号：US12224252B2

公开(公告)日：2025-02-11

申请号：US17030121

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  William J. Lambert ,  Haifa Hariri ,  Siddharth Kulasekaran ,  Mathew Manusharow ,  Anne Augustine

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552

Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

公开(公告)号：US20240063183A1

公开(公告)日：2024-02-22

申请号：US17820982

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Anne Augustine ,  Beomseok Choi ,  Kimin Jun ,  Omkar G. Karhade ,  Shawna M. Liff ,  Julien Sebot ,  Johanna M. Swan ,  Krishna Vasanth Valavala

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L24/08 ,  H01L24/16 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/80 ,  H01L23/481 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/37001 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.

公开(公告)号：US20220240370A1

公开(公告)日：2022-07-28

申请号：US17720171

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Huong T. Do ,  Anne Augustine

IPC: H05K1/02 ,  H05K1/16 ,  H01L23/367 ,  H01L23/498 ,  H01F27/28 ,  H01F41/04 ,  H01L21/48 ,  H05K1/18

Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

公开(公告)号：US11357096B2

公开(公告)日：2022-06-07

申请号：US16027737

申请日：2018-07-05

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Huong T. Do ,  Anne Augustine

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H01L23/367 ,  H01L23/498 ,  H01F27/28 ,  H01F41/04 ,  H01L21/48 ,  H05K1/18

Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

公开(公告)号：US11335620B2

公开(公告)日：2022-05-17

申请号：US16035129

申请日：2018-07-13

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Anne Augustine ,  Huong Do ,  William Lambert

IPC: H01L23/367 ,  H01L23/64 ,  H01L23/32 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/522

Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.

公开(公告)号：US20200020652A1

公开(公告)日：2020-01-16

申请号：US16035129

申请日：2018-07-13

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Anne Augustine ,  Huong Do ,  William Lambert

IPC: H01L23/64 ,  H01L23/32 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.

公开(公告)号：US11690165B2

公开(公告)日：2023-06-27

申请号：US17720171

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Huong T. Do ,  Anne Augustine

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H01L23/367 ,  H01L23/498 ,  H01F27/28 ,  H01F41/04 ,  H01L21/48 ,  H05K1/18

CPC classification number: H05K1/0204 ,  H01F27/2804 ,  H01F41/041 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/367 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/165 ,  H05K1/181 ,  H01F2027/2809 ,  H05K2201/09672 ,  H05K2201/1003 ,  H05K2201/10166 ,  H05K2201/10515 ,  H05K2201/10734

Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

公开(公告)号：US20220293327A1

公开(公告)日：2022-09-15

申请号：US17199005

申请日：2021-03-11

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Sri Chaitra Jyotsna Chavali ,  Robert L. Sankman ,  Anne Augustine ,  Kaladhar Radhakrishnan

IPC: H01F27/26 ,  H01F27/40 ,  H01F41/04

Abstract: An inductor can be formed in a coreless electronic substrate, such that the fabrication process does not result in the magnetic material used in the inductor leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming conductive vias with a lithographic process, rather than a standard laser process, in combination with panel planarization to prevent exposure of the magnetic material to the plating and/or etching solutions/chemistries.

公开(公告)号：US20200015348A1

公开(公告)日：2020-01-09

申请号：US16027737

申请日：2018-07-05

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Huong T. Do ,  Anne Augustine

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/16 ,  H01L23/367 ,  H01L23/498 ,  H01F27/28 ,  H01F41/04 ,  H01L21/48

Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.