公开(公告)号：US12020054B2

公开(公告)日：2024-06-25

申请号：US17256204

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Kun Tian ,  Ankur Shah ,  David Cowperthwaite ,  Zhi Wang ,  Zhenyu Wang ,  Kalyan Kondapally ,  Jonathan Bloomfield ,  Wei Zhang

IPC: G06F9/455 ,  G06F3/14 ,  G06F9/4401 ,  G06F9/451 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395

CPC classification number: G06F9/45558 ,  G06F3/1407 ,  G06F9/4411 ,  G06F9/452 ,  G06F9/455 ,  G09G5/001 ,  G09G5/006 ,  G06F2009/45562 ,  G06F2009/45595 ,  G09G5/393 ,  G09G5/395

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

公开(公告)号：US20230298129A1

公开(公告)日：2023-09-21

申请号：US17849165

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  David Cowperthwaite ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/1009 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/1009 ,  G06T1/20 ,  G06F2212/302

Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

公开(公告)号：US20230298128A1

公开(公告)日：2023-09-21

申请号：US17849106

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Aditya Navale ,  David Cowperthwaite

IPC: G06T1/60 ,  G06F12/1027 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/1027 ,  G06T1/20 ,  G06F2212/302 ,  G06F2212/683

Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table.

公开(公告)号：US11354171B2

公开(公告)日：2022-06-07

申请号：US17131648

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  David Cowperthwaite ,  Abhishek R. Appu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Altug Koker ,  Balaji Vembu

IPC: G06F9/50 ,  G06F1/329

Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.

公开(公告)号：US20210182120A1

公开(公告)日：2021-06-17

申请号：US17131648

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  David Cowperthwaite ,  Abhishek R. Appu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Altug Koker ,  Balaji Vembu

IPC: G06F9/50

Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.

公开(公告)号：US20230306552A1

公开(公告)日：2023-09-28

申请号：US17827305

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  David Puffer ,  Ankur Shah ,  Alan Previn Teres Alexis ,  Satyeshwar Singh

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/455

CPC classification number: G06T1/20 ,  G06F9/455 ,  G06T15/005

Abstract: Described herein is a partitional graphics processor including a display controller including hardware display virtualization. One embodiment provides a graphics processor comprising a system interface including a first virtual interface and a second virtual interface, a render engine to perform graphics rendering operations, and a display engine including hardware display virtualization. The render engine is configured to perform a first rendering operation in response to a command received via the first virtual interface and a second rendering operation in response to a command received via the second virtual interface. The display engine configured to present output of the first rendering operation via a first physical display plane that is associated with the first virtual interface and present output of the second rendering operation via a second physical display plane that is associated with the second virtual interface.

公开(公告)号：US20230298125A1

公开(公告)日：2023-09-21

申请号：US17827444

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Jeffery S. Boles ,  David Cowperthwaite ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Aravindh Anantaraman ,  Michael Apodaca ,  Kenneth Daxer

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T1/60 ,  G06F9/4881 ,  G06F9/5061 ,  G06F9/505 ,  G06T2200/16

Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

公开(公告)号：US20230297440A1

公开(公告)日：2023-09-21

申请号：US17827373

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Jeffery S. Boles ,  Hema Chand Nalluri ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala

IPC: G06F9/50 ,  G06T1/20

CPC classification number: G06F9/5077 ,  G06F9/5016 ,  G06T1/20

Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

公开(公告)号：US20230297421A1

公开(公告)日：2023-09-21

申请号：US17827346

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Hema Chand Nalluri ,  Jeffery S. Boles ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Michael Apodaca

IPC: G06F9/48 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06T1/60 ,  G06T1/20 ,  G06F9/5038 ,  G06F9/5055

Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.

公开(公告)号：US20220138286A1

公开(公告)日：2022-05-05

申请号：US17133336

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： David Zage ,  Scott Janus ,  Ned M. Smith ,  Vidhya Krishnan ,  Siddhartha Chhabra ,  Rajesh Poornachandran ,  Tomer Levy ,  Julien Carreno ,  Ankur Shah ,  Ronald Silvas ,  Aravindh Anantaraman ,  David Puffer ,  Vedvyas Shanbhogue ,  David Cowperthwaite ,  Aditya Navale ,  Omer Ben-Shalom ,  Alex Nayshtut ,  Xiaoyu Ruan

IPC: G06F21/10 ,  G06F21/60 ,  G06T1/20 ,  G06F9/455

Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.