公开(公告)号：US20180096955A1

公开(公告)日：2018-04-05

申请号：US15283327

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Minsoo Lee ,  Gordon A. Haller ,  Philip J. Ireland

IPC: H01L23/58 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/3205

CPC classification number: H01L23/585 ,  H01L21/3065 ,  H01L21/32051 ,  H01L23/53271 ,  H01L23/562 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3512

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

公开(公告)号：US09520402B1

公开(公告)日：2016-12-13

申请号：US14835648

申请日：2015-08-25

Applicant: Intel Corporation

Inventor： Gordon A. Haller ,  Jun Liu

IPC: H01L27/115 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3205

CPC classification number: H01L27/11551 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76889 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: Embodiments of the present disclosure are directed towards techniques to provide etch stops to the wordlines that form a staircase structure of a 3D memory array. In one embodiment, the apparatus may comprise a 3D memory array having wordlines disposed in a staircase structure. A wordline may include a silicide layer and a spacer disposed to abut the silicide layer around an end of the wordline. The silicide layer and the spacer may form an etch stop of the wordline for a wordline contact structure to electrically connect the wordline with the memory array in response to a deposition of the wordline contact structure on the etch stop. The etch stop may be configured to prevent a physical or electrical contact of the wordline contact structure with an adjacent wordline of the staircase structure, in order to avoid undesired short circuits. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及向形成3D存储器阵列的阶梯结构的字线提供蚀刻停止点的技术。 在一个实施例中，该装置可以包括具有设置在阶梯结构中的字线的3D存储器阵列。 字线可以包括硅化物层和设置成邻近字线的端部处的硅化物层的间隔物。 硅化物层和间隔物可以形成用于字线接触结构的字线的蚀刻停止物，以响应于刻蚀停止处的字线接触结构的沉积而将字线与存储器阵列电连接。 蚀刻停止件可以被配置为防止字线触点结构与阶梯结构的相邻字线的物理或电接触，以避免不期望的短路。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10453829B2

公开(公告)日：2019-10-22

申请号：US15625350

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Merri Lyn Carlson ,  Hongbin Zhu ,  Gordon A. Haller ,  James E. Davis ,  Kevin G. Duesman ,  James Mathew ,  Michael P. Violette

IPC: H01L27/11556 ,  H01L25/10 ,  H01L27/11529 ,  H01L27/11548

Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.

公开(公告)号：US09857989B1

公开(公告)日：2018-01-02

申请号：US15283296

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G11C16/06 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.

公开(公告)号：US11018097B2

公开(公告)日：2021-05-25

申请号：US16707188

申请日：2019-12-09

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Minsoo Lee ,  Gordon A. Haller ,  Philip J. Ireland

IPC: H01L23/58 ,  H01L23/532 ,  H01L21/3065 ,  H01L21/3205 ,  H01L23/00

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

公开(公告)号：US11010058B2

公开(公告)日：2021-05-18

申请号：US16436917

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damaria ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US20180366453A1

公开(公告)日：2018-12-20

申请号：US15625350

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Merri Lyn Carlson ,  Hongbin Zhu ,  Gordon A. Haller ,  James E. Davis ,  Kevin G. Duesman ,  James Mathew ,  Michael P. Violette

IPC: H01L25/10 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L25/105 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556

Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.

公开(公告)号：US20180307412A1

公开(公告)日：2018-10-25

申请号：US15860540

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US20180190540A1

公开(公告)日：2018-07-05

申请号：US15396469

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Jun Liu ,  Gordon A. Haller ,  Fei Wang ,  Wei Yeeng Ng ,  Wesley O. McKinsey ,  Zhiqiang Xie ,  Jeremy F. Adams ,  Hongbin Zhu ,  Jun Zhao ,  Mark A. Levan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

公开(公告)号：US10707121B2

公开(公告)日：2020-07-07

申请号：US15396469

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Jun Liu ,  Mark A. Levan ,  Gordon A. Haller ,  Fei Wang ,  Wei Yeeng Ng ,  Wesley O. McKinsey ,  Zhiqiang Xie ,  Jeremy F. Adams ,  Hongbin Zhu ,  Jun Zhao

IPC: H01L21/768 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11548 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.