公开(公告)号：US09761713B2

公开(公告)日：2017-09-12

申请号：US14941291

申请日：2015-11-13

Applicant: INTEL CORPORATION

Inventor： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51

CPC classification number: H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

公开(公告)号：US10741669B2

公开(公告)日：2020-08-11

申请号：US15859355

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Jenny Hu ,  Anindya Dasgupta ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.

公开(公告)号：US10727313B2

公开(公告)日：2020-07-28

申请号：US15859356

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Jenny Hu ,  Anindya Dasgupta ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

公开(公告)号：US10573747B2

公开(公告)日：2020-02-25

申请号：US15377994

申请日：2016-12-13

Applicant: INTEL CORPORATION

Inventor： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/8234

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

公开(公告)号：US20160155843A1

公开(公告)日：2016-06-02

申请号：US14941291

申请日：2015-11-13

Applicant: INTEL CORPORATION

Inventor： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

公开(公告)号：US10854732B2

公开(公告)日：2020-12-01

申请号：US16908468

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Jenny Hu ,  Anindya Dasgupta ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G11C7/04 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

公开(公告)号：US11476334B2

公开(公告)日：2022-10-18

申请号：US16957055

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Orb Acton ,  Joseph Steigerwald ,  Anand Murthy ,  Scott Maddox ,  Jenny Hu

IPC: H01L29/10 ,  H01L21/28 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.

公开(公告)号：US20200343343A1

公开(公告)日：2020-10-29

申请号：US16957055

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Orb Acton ,  Joseph Steigerwald ,  Anand Murthy ,  Scott Maddox ,  Jenny Hu

IPC: H01L29/10 ,  H01L29/49 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.

公开(公告)号：US20170092542A1

公开(公告)日：2017-03-30

申请号：US15377994

申请日：2016-12-13

Applicant: INTEL CORPORATION

Inventor： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC: H01L21/8234 ,  H01L27/088

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

公开(公告)号：US09219155B2

公开(公告)日：2015-12-22

申请号：US14108265

申请日：2013-12-16

Applicant: Intel Corporation

Inventor： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了多阈值电压装置及相关联的技术和配置。 在一个实施例中，一种装置包括半导体衬底，设置在半导体衬底上的沟道体，具有与沟道本体耦合的第一厚度的第一栅电极和具有与沟道本体耦合的第二厚度的第二栅电极，其中， 第一厚度大于第二厚度。 可以描述和/或要求保护其他实施例。