公开(公告)号：US10930557B2

公开(公告)日：2021-02-23

申请号：US16819590

申请日：2020-03-16

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US10141226B2

公开(公告)日：2018-11-27

申请号：US15827491

申请日：2017-11-30

申请人： INTEL CORPORATION

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45 ,  H01L29/16 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L29/08 ,  H01L21/283 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/49

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US09997563B2

公开(公告)日：2018-06-12

申请号：US15596650

申请日：2017-05-16

申请人： Intel Corporation

发明人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC分类号： H01L27/22 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

公开(公告)号：US09761713B2

公开(公告)日：2017-09-12

申请号：US14941291

申请日：2015-11-13

申请人： INTEL CORPORATION

发明人： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51

CPC分类号： H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645

摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

公开(公告)号：US09660181B2

公开(公告)日：2017-05-23

申请号：US13994715

申请日：2013-03-15

申请人： Intel Corporation

发明人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC分类号： H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

公开(公告)号：US20190051558A1

公开(公告)日：2019-02-14

申请号：US16162186

申请日：2018-10-16

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/16 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/311 ,  H01L29/08 ,  H01L29/49 ,  H01L23/535 ,  H01L21/285 ,  H01L21/283 ,  H01L23/522 ,  H01L23/528

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US09972541B2

公开(公告)日：2018-05-15

申请号：US15328473

申请日：2014-08-29

申请人： Intel Corporation

发明人： Joseph M. Steigerwald ,  Nick Lindert

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L21/304 ,  H01L21/308 ,  H01L23/535 ,  H01L29/66

CPC分类号： H01L21/823475 ,  H01L21/304 ,  H01L21/3085 ,  H01L21/823431 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of the present disclosure describe techniques for filling a high aspect ratio, narrow structure with multiple metal layers and associated configurations. In one embodiment, an apparatus includes a transistor structure comprising a semiconductor material, a dielectric material having a recess defined over the transistor structure, the recess having a height in a first direction, an electrode terminal disposed in the recess and coupled with the transistor structure, wherein a first portion of the electrode terminal comprises a first metal in direct contact with the transistor structure and a second portion of the electrode terminal comprises a second metal disposed on the first portion and wherein an interface between the first portion and the second portion is planar and extends across the recess in a second direction that is substantially perpendicular to the first direction. Other embodiments may be described and/or claimed.

公开(公告)号：US09508821B2

公开(公告)日：2016-11-29

申请号：US14998092

申请日：2015-12-23

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/51 ,  H01L29/16 ,  H01L29/45 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423 ,  H01L23/522 ,  H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L21/283 ,  H01L23/528 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US11600524B2

公开(公告)日：2023-03-07

申请号：US17147423

申请日：2021-01-12

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US10573747B2

公开(公告)日：2020-02-25

申请号：US15377994

申请日：2016-12-13

申请人： INTEL CORPORATION

发明人： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/8234

摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.