公开(公告)号：US20240177918A1

公开(公告)日：2024-05-30

申请号：US18071237

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Mohammad Mamunur RAHMAN

IPC: H01F27/28 ,  H01F27/30 ,  H01F41/04 ,  H01L23/08 ,  H01L23/31

CPC classification number: H01F27/2804 ,  H01F27/306 ,  H01F41/041 ,  H01L23/08 ,  H01L23/3128 ,  H01F2027/2809 ,  H01F2027/2819

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate, a first opening through the core substrate, a second opening through the core substrate and adjacent to the first opening, and a first structure around the core substrate between the first opening and the second opening. In an embodiment, the first structure is electrically conductive. The package core may further comprise a second structure around the core substrate outside of the first opening and the second opening, where the second structure is electrically conductive.

公开(公告)号：US20240063069A1

公开(公告)日：2024-02-22

申请号：US17892930

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Rahul N. MANEPALLI ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/15

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/15 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates with glass cores. In an embodiment, a core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass, In an embodiment, through glass vias (TGVs) pass through the substrate, and notches are formed into the first surface and the second surface of the substrate.

公开(公告)号：US20230091720A1

公开(公告)日：2023-03-23

申请号：US17482926

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Mohammad Mamunur RAHMAN ,  Jeremy D. ECTON ,  Je-Young CHANG

IPC: H01L23/473 ,  H01L23/367 ,  H01L21/48

Abstract: A system includes a package layer with microchannels to spread heat localized in the package at an electronic die. The microchannel is integrated onto or into the package layer. The microchannel has a hollow heat conducting material with a rectangular cross-section through which a fluid is to flow to spread the heat. The microchannel can be an open channel that is sealed with a pump to cause the fluid to flow through the microchannel. The microchannel can be sealed in the integration process to result in a closed heat pipe structure in which liquid flows through expansion and compression in response to heating and cooling, respectively.

公开(公告)号：US20230057384A1

公开(公告)日：2023-02-23

申请号：US17408157

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Hiroki TANAKA ,  Jason M. GAMBA ,  Srinivas V. PIETAMBARAM

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments disclosed herein include carriers and methods of using the carriers to assemble electronic packages. In an embodiment, a carrier for electronic packaging assembly comprises a mold layer with a first surface and a second surface. In an embodiment, a plurality of glass substrates are embedded in the mold layer. In an embodiment, individual ones of the glass substrates comprise a third surface and a fourth surface, where the third surface of the glass substrate is substantially coplanar with the first surface of the mold layer.

公开(公告)号：US20220310518A1

公开(公告)日：2022-09-29

申请号：US17213147

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Haobo CHEN ,  Xiaoying GUO ,  Hongxia FENG ,  Kristof DARMAWIKARTA ,  Bai NIE ,  Tarek A. IBRAHIM ,  Gang DUAN ,  Jeremy D. ECTON ,  Sheng C. LI ,  Leonel ARANA

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

公开(公告)号：US20250004380A1

公开(公告)日：2025-01-02

申请号：US18215427

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Joseph BLOXHAM ,  Jeremy D. ECTON

IPC: G03F7/30

Abstract: Devices, systems, and methods for conditioning a solvent return flow from a photolithographic process used for semiconductor processing are presented. Reuse of materials in semiconductor processing can provide environmental and manufacturing cost advantages. Devices for conditioning a solvent return flow from a photolithographic process and systems for photolithographic processes include a baffle system and a light system. Methods for reusing a solvent from a photolithographic process include passing the solvent through a conditioning device having a baffle system and a light system.

公开(公告)号：US20240222137A1

公开(公告)日：2024-07-04

申请号：US18091022

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Shaojiang CHEN ,  Jeremy D. ECTON ,  Oladeji FADAYOMI ,  Srinivas V. PIETAMBARAM ,  Matthew L. TINGEY

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L21/3213 ,  H01L21/76808 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core, where a top surface of the TGV is not coplanar with a top surface of the core. In an embodiment, the electronic package further comprises a ridge on the top surface of the TGV, where the ridge is symmetric about a centerline of the TGV.

公开(公告)号：US20240071883A1

公开(公告)日：2024-02-29

申请号：US17893893

申请日：2022-08-23

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/544

CPC classification number: H01L23/49827 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

公开(公告)号：US20240055345A1

公开(公告)日：2024-02-15

申请号：US17886278

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI

IPC: H01L23/522 ,  H01L49/02 ,  H01G11/70 ,  H01L23/15

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01G11/70 ,  H01L23/15

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a pillar is over the substrate, and a capacitor is over the pillar. In an embodiment, the capacitor comprises a first conductive layer on the pillar, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer.

公开(公告)号：US20230093258A1

公开(公告)日：2023-03-23

申请号：US17482830

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Haobo CHEN ,  Leonel ARANA

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/48

Abstract: Embodiments include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first substrate, and a second substrate coupled to the first substrate. In an embodiment, the second substrate comprises a core, and the core comprises an organic material. In an embodiment, a third substrate is coupled to the second substrate, and the third substrate comprises a glass layer.