公开(公告)号：US20240282591A1

公开(公告)日：2024-08-22

申请号：US18171683

申请日：2023-02-21

Applicant: Intel Corporation

Inventor： Oladeji FADAYOMI ,  Shaojiang CHEN ,  Jeremy ECTON ,  Matthew TINGEY ,  Srinivas PIETAMBARAM ,  Leonel ARANA

IPC: H01L21/48 ,  C23F1/02

CPC classification number: H01L21/486 ,  C23F1/02

Abstract: The present disclosure is directed to a planarization tool having at least one module with a target holder for supporting a target with a metal layer, at least one of a plurality of etch inhibitor dispensers for discharging an etch inhibitor toward the target, and a plurality of nozzles for discharging a chemical etchant at an angle towards the target to perform selective removal of the metal layer for planarization of the target. In an aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be combined as a single unit to discharge the chemical etchant and the etch inhibitor together. In another aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be configured in a single module or separate modules.

公开(公告)号：US20240222130A1

公开(公告)日：2024-07-04

申请号：US18091026

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Shaojiang CHEN ,  Jeremy D. ECTON ,  Oladeji FADAYOMI ,  Hsin-Wei WANG ,  Changhua LIU ,  Bin MU ,  Hongxia FENG ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM

IPC: H01L21/306 ,  H01L21/321 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L21/30604 ,  H01L21/3212 ,  H01L21/486 ,  H01L21/7688 ,  H01L21/76898 ,  H01L21/268

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core. In an embodiment, the TGV comprises a top surface that is non-planar and includes a symmetric ridge on the non-planar top surface.

公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20240222137A1

公开(公告)日：2024-07-04

申请号：US18091022

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Shaojiang CHEN ,  Jeremy D. ECTON ,  Oladeji FADAYOMI ,  Srinivas V. PIETAMBARAM ,  Matthew L. TINGEY

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L21/3213 ,  H01L21/76808 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core, where a top surface of the TGV is not coplanar with a top surface of the core. In an embodiment, the electronic package further comprises a ridge on the top surface of the TGV, where the ridge is symmetric about a centerline of the TGV.