公开(公告)号：US20240113194A1

公开(公告)日：2024-04-04

申请号：US17957580

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Mekha George ,  Seda Cekli ,  Kilhyun Bang ,  Krishna Ganesan

IPC: H01L29/423 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/31116 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696

Abstract: Materials and techniques for recessing heterogenous materials in integrated circuit (IC) dies. A first etch may reveal a surface at a desired depth, and a second etch may remove material laterally to reveal sidewalls down to the desired depth of the recess. The first etch may be a cyclical etch, and the second etch may be a continuous etch. The first and second etches may occur in a same chamber. The first and second etches may each be selective to materials with similarities. An IC die may have different, substantially coplanar materials at a recessed surface between and below sidewalls of another material. The recess may have squared profile. The recess may be over transistor structures.

公开(公告)号：US20230282717A1

公开(公告)日：2023-09-07

申请号：US17687032

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Nikhil J. Mehta ,  Krishna Ganesan ,  Chanaka D. Munasinghe ,  Tahir Ghani ,  Charles H. Wallace

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/401

Abstract: Techniques are provided herein to form semiconductor devices that use uniform topside dielectric plugs as masking structures to form conductive contacts to various source or drain regions. In an example, a plurality of semiconductor devices each include one or more semiconductor regions extending in a first direction between corresponding source or drain regions. The source or drain regions are adjacent to one another along a second direction different from the first direction. Conductive contacts are formed over the source or drain regions of the semiconductor devices. A dielectric fill is between one or more adjacent pairs of conductive contacts and dielectric masking structures having a substantially uniform thickness are present over the dielectric fill between adjacent pairs of conductive contacts. This uniform thickness characteristic applies to all of the masking structures regardless of their length along the second direction.

公开(公告)号：US20240222447A1

公开(公告)日：2024-07-04

申请号：US18090048

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Reken Patel ,  Conor P. Puls ,  Krishna Ganesan ,  Akitomo Matsubayashi ,  Diana Ivonne Paredes ,  Sunzida Ferdous ,  Brian Greene ,  Lateef Uddin Syed ,  Kyle T. Horak ,  Lin Hu ,  Anupama Bowonder ,  Swapnadip Ghosh ,  Amritesh Rai ,  Shruti Subramanian ,  Gordon S. Freeman

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28123 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit includes a first device, and a laterally adjacent second device. The first device includes a first body of semiconductor material extending laterally from a first source or drain region, a first gate structure on the first body, and a first contact extending vertically upward from the first source or drain region. The second device includes a second body of semiconductor material extending laterally from a second source or drain region, a second gate structure on the second body, and a second contact extending vertically upward from the second source or drain region. A gate cut structure including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact. In some examples, a third contact extends laterally from the first contact to the second contact and passes over the gate cut structure.

公开(公告)号：US20250089228A1

公开(公告)日：2025-03-13

申请号：US18464392

申请日：2023-09-11

Applicant: Intel Corporation

Inventor： Meenakshisundaram Ramanathan ,  Krishna Ganesan ,  John Crocker ,  Akitomo Matsubayashi ,  Jianhua Yin ,  Reken Patel

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: Integrated circuit (IC) structures that include static random-access memory (SRAM) and that are fabricated using gate contact patterning after source/drain (S/D) metallization are disclosed. An example IC structure includes a transistor comprising an S/D region and a gate electrode material, an S/D contact in electrical contact with the S/D region, and a gate contact in electrical contact with the gate electrode material. The S/D contact includes a first electrically conductive material, the gate contact includes a second electrically conductive material, and a portion of the second electrically conductive material is in electrical contact with a portion of the first electrically conductive material, wherein an average grain size or orientation in the portion of the first electrically conductive material is different from an average grain size or orientation in the portion of the second electrically conductive material.

公开(公告)号：US20240321872A1

公开(公告)日：2024-09-26

申请号：US18125447

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Thomas Obrien ,  Krishna Ganesan ,  Ankit Kirit Lakhani ,  Prabhjot Kaur Luthra ,  Nidhi Khandelwal ,  Clifford J. Engel ,  Baofu Zhu ,  Meenakshisundaram Ramanathan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.