公开(公告)号：US20240290680A1

公开(公告)日：2024-08-29

申请号：US18115711

申请日：2023-02-28

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L23/367 ,  H01L21/4871 ,  H01L23/3736

Abstract: A low-profile memory apparatus that is compatible with system thermal solutions. The apparatus includes a substrate layer with an upper surface and a lower surface, a portion of the substrate layer having a first arrangement of conductive contacts located on the lower surface. A memory package is inverted and attached to the first arrangement of conductive contacts. A heat spreader component comprising a cavity is included. The memory package and the portion of the substrate layer having the first arrangement of conductive contacts located in the cavity. A second arrangement of conductive contacts is located on the lower surface of the substrate layer, external to the heat spreader component, to attach the apparatus to another substrate or printed circuit board in a multi-die assembly.

公开(公告)号：US11908793B2

公开(公告)日：2024-02-20

申请号：US17716937

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh ,  Amruthavalli Pallavi Alur ,  Debendra Mallik

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2924/01029

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20250113428A1

公开(公告)日：2025-04-03

申请号：US18478967

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  Tin Poay Chuah ,  Kavitha Nagarajan ,  Telesphor Kamgaing ,  Poh Boon Khoo ,  Jiun Hann Sir

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H05K3/40

Abstract: Technologies for a shield for electromagnetic interference include a circuit board with an integrated circuit package on it, with a hole in the circuit board under the integrated circuit package. The integrated circuit package may include one or more dies or other components on the underside of the package, at least partially positioned in the hole in the circuit board. An electromagnetic shield box can be positioned in the hole. Tabs of the electromagnetic shield box may interface with pads on the same side of the circuit board as the integrated circuit package. The electromagnetic shield box may prevent or reduce electromagnetic or radiofrequency interference on the components of the integrated circuit package. Positioning the electromagnetic shield box can reduce the overall height of the circuit board, among other advantages.

公开(公告)号：US20230091395A1

公开(公告)日：2023-03-23

申请号：US17483670

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Mooi Ling Chang ,  Poh Boon Khoo ,  Chu Aun Lim ,  Min Suet Lim ,  Prabhat Ranjan

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: Integrated circuit (IC) packages with On Package Memory (OPM) architectures are disclosed herein. An example IC package includes a substrate having a first side and a second side opposite the first side, a semiconductor die mounted on the first side of the substrate, and a die pad on the first side of the substrate. The die is electrically coupled to the die pad. The IC package also includes a memory pad on the first side of the substrate. The memory pad is to be electrically coupled to a memory mounted on the first side of the substrate. The IC package further includes a ball on the second side of the substrate, and a memory interconnect in the substrate electrically coupling the die pad, the memory pad, and the ball.

公开(公告)号：US20230369232A1

公开(公告)日：2023-11-16

申请号：US17741988

申请日：2022-05-11

Applicant: Intel Corporation

Inventor： Hazwani Jaffar ,  Poh Boon Khoo ,  Hooi San Lam ,  Jiun Hann Sir ,  Eng Huat Goh

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L25/18 ,  H01L25/50 ,  H01L21/4853 ,  H01L25/105

Abstract: An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC. The companion component includes a second substrate, second solder bumps, and third solder bumps. The second solder bumps include a second solder bump surface, and the third solder bumps include a third solder bump surface at a different height than the second solder bump surface. The second solder bump surface contacts the top surface of the first substrate and the third solder bump surface is at a same height as the first solder bump surface.

公开(公告)号：US11658111B2

公开(公告)日：2023-05-23

申请号：US17200700

申请日：2021-03-12

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh ,  Amruthavalli Pallavi Alur ,  Debendra Mallik

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2924/01029

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US11699644B2

公开(公告)日：2023-07-11

申请号：US17529093

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/552

Abstract: A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.

公开(公告)号：US11205613B2

公开(公告)日：2021-12-21

申请号：US16912653

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.

公开(公告)号：US20200328151A1

公开(公告)日：2020-10-15

申请号：US16384348

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh ,  Amruthavalli Pallavi Alur ,  Debendra Mallik

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20250107003A1

公开(公告)日：2025-03-27

申请号：US18475920

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Chin Mian Choong ,  Jiun Hann Sir ,  Poh Boon Khoo ,  Wei Jern Tan ,  Boon Ping Koh

IPC: H05K1/18 ,  H01L23/498 ,  H01L25/18 ,  H05K1/14 ,  H05K3/40 ,  H05K3/46 ,  H10B80/00

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed comprising: an integrated circuit package including a package substrate, the package substrate including a first contact and a second contact, the first contact to be electrically coupled to a printed circuit board (PCB); and a timing package distinct from the integrated circuit package, the timing package including a third contact, the third contact to be electrically coupled to the second contact independent of the PCB.