公开(公告)号：US20220102521A1

公开(公告)日：2022-03-31

申请号：US17033471

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Nazila HARATIPOUR ,  Siddharth CHOUKSEY ,  Jack T. KAVALIEROS ,  Jitendra Kumar JHA ,  Matthew V. METZ ,  Mengcheng LU ,  Anand S. MURTHY ,  Koustav GANGULY ,  Ryan KEECH ,  Glenn A. GLASS ,  Arnab SEN GUPTA

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US20210091181A1

公开(公告)日：2021-03-25

申请号：US16580941

申请日：2019-09-24

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/167 ,  H01L29/417 ,  H01L29/78

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20200312842A1

公开(公告)日：2020-10-01

申请号：US16368077

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Nicholas MINUTILLO ,  Anand MURTHY ,  Aaron BUDREVICH ,  Peter WELLS

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/167 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L23/00

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

公开(公告)号：US20240014268A1

公开(公告)日：2024-01-11

申请号：US18370586

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66439

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20200312958A1

公开(公告)日：2020-10-01

申请号：US16367134

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Anand MURTHY ,  Ryan KEECH ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/00

Abstract: Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20240170484A1

公开(公告)日：2024-05-23

申请号：US18425944

申请日：2024-01-29

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Nicholas MINUTILLO ,  Anand MURTHY ,  Aaron BUDREVICH ,  Peter WELLS

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/00 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

公开(公告)号：US20210408246A1

公开(公告)日：2021-12-30

申请号：US16911771

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Koustav GANGULY ,  Ryan KEECH ,  Subrina RAFIQUE ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Ehren MANNEBACH ,  Mauro KOBRINSKY ,  Gilbert DEWEY

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

公开(公告)号：US20240347610A1

公开(公告)日：2024-10-17

申请号：US18757013

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Koustav GANGULY ,  Ryan KEECH ,  Subrina RAFIQUE ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Ehren MANNEBACH ,  Mauro KOBRINSKY ,  Gilbert DEWEY

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28556 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41766 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

公开(公告)号：US20240258427A1

公开(公告)日：2024-08-01

申请号：US18605406

申请日：2024-03-14

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Benjamin CHU-KUNG ,  Subrina RAFIQUE ,  Devin MERRILL ,  Ashish AGRAWAL ,  Harold KENNEL ,  Yang CAO ,  Dipanjan BASU ,  Jessica TORRES ,  Anand MURTHY

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20210408284A1

公开(公告)日：2021-12-30

申请号：US16912136

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Ashish AGRAWAL ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Koustav GANGULY ,  Ryan KEECH ,  Siddharth CHOUKSEY ,  Willy RACHMADY

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165

Abstract: Gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, and methods of fabricating gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, are described. For example, an integrated circuit structure includes an insulator layer above a substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator layer. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and on the insulator layer. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires. The gate stack includes a high-k dielectric layer continuous with and having a same composition as the insulator layer.