公开(公告)号：US20250113586A1

公开(公告)日：2025-04-03

申请号：US18374929

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Rahul PANDEY ,  Yang CAO ,  Rahul RAMAMURTHY ,  Jubin NATHAWAT ,  Michael L. HATTENDORF ,  Jae HUR ,  Anant H. JAHAGIRDAR ,  Steven R. NOVAK ,  Tao CHU ,  Yanbin LUO ,  Minwoo JANG ,  Paul A. PACKAN ,  Owen Y. LOH ,  David J. TOWNER

IPC: H01L29/51 ,  H01L21/3115 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit structure comprises a fin extending from a substrate, the fin comprising source and drain regions, and a channel region between the source and drain regions. A multilayer high-k gate stack comprising a plurality of materials extends conformally over the fin over the channel region. A gate electrode is over and on a topmost material in the multilayer high-k gate stack. Fluorine is implanted in the substrate beneath the multilayer high-k gate stack or in the plurality of materials comprising the multilayer high-k gate stack.

公开(公告)号：US20220059467A1

公开(公告)日：2022-02-24

申请号：US17517472

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Yang CAO ,  Akm Shaestagir CHOWDHURY ,  Jeff GRUNES

IPC: H01L23/532 ,  H01L21/288 ,  H01L21/768

Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

公开(公告)号：US20210026234A1

公开(公告)日：2021-01-28

申请号：US16521445

申请日：2019-07-24

Applicant: Intel Corporation

Inventor： John MAGANA ,  Guojing ZHANG ,  Yang CAO

IPC: G03F1/24 ,  G03F7/20

Abstract: Embodiments disclosed herein include EUV reticles and methods of forming such reticles. In an embodiment a method of forming an EUV reticle comprises providing a reticle, where the reticle comprises, a substrate, a mirror layer over the substrate, where the mirror layer comprises a plurality of first mirror layers and second mirror layers in an alternating pattern, and a capping layer over the mirror layer. In an embodiment, the method may further comprise disposing a first layer over the capping layer, patterning an opening in the first layer, and disposing a second layer in the opening, where the second layer is disposed with an electroless deposition process.

公开(公告)号：US20240258427A1

公开(公告)日：2024-08-01

申请号：US18605406

申请日：2024-03-14

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Benjamin CHU-KUNG ,  Subrina RAFIQUE ,  Devin MERRILL ,  Ashish AGRAWAL ,  Harold KENNEL ,  Yang CAO ,  Dipanjan BASU ,  Jessica TORRES ,  Anand MURTHY

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20200313001A1

公开(公告)日：2020-10-01

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Benjamin CHU-KUNG ,  Subrina RAFIQUE ,  Devin MERRILL ,  Ashish AGRAWAL ,  Harold KENNEL ,  Yang CAO ,  Dipanjan BASU ,  Jessica TORRES ,  Anand MURTHY

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.