公开(公告)号：US20220165585A1

公开(公告)日：2022-05-26

申请号：US17669288

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Vipul MEHTA ,  Edvin CETEGEN ,  Yuying WEI ,  Sushrutha GUJJULA ,  Nisha ANANTHAKRISHNAN ,  Shan ZHONG

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.

公开(公告)号：US20190304808A1

公开(公告)日：2019-10-03

申请号：US15942109

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Vipul MEHTA ,  Edvin CETEGEN ,  Yuying WEI ,  Sushrutha GUJJULA ,  Nisha ANANTHAKRISHNAN ,  Shan ZHONG

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.

公开(公告)号：US20190006325A1

公开(公告)日：2019-01-03

申请号：US16127004

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： Weng Hong TEH ,  John S. GUZEK ,  Shan ZHONG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/12 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L23/13

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

公开(公告)号：US20170025392A1

公开(公告)日：2017-01-26

申请号：US15289058

申请日：2016-10-07

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  John S. GUZEK ,  Shan ZHONG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

Abstract translation: 描述了封装组件和封装集成电路芯片的方法。 公开的封装组件具有包括IC芯片的间隔件和凹陷区域。 提供了建立结构，使得能够例如三维（3D）封装（或封装（SiP）或多芯片模块系统）），片上3D封装和混合3D绑定。 本发明的实施例可以用于例如创建逻辑到存储器，存储器到存储器和逻辑到逻辑接口堆叠组件。