公开(公告)号：US20210303357A1

公开(公告)日：2021-09-30

申请号：US16833595

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

公开(公告)号：US20190114434A1

公开(公告)日：2019-04-18

申请号：US16229496

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Haifeng GONG ,  Vasudevan SRINIVASAN ,  Antonio J. HASBUN MARIN

IPC: G06F21/57 ,  G06F21/60 ,  H04L9/32

Abstract: A system includes a processor coupled to an integrated circuit. The processor includes a non-volatile memory to store instructions to perform a boot process. The boot process is discontinued to prevent unauthorized use of the processor if a value received from the integrated circuit in response to a first value sent to the integrated is not valid.

公开(公告)号：US20220244996A1

公开(公告)日：2022-08-04

申请号：US17717859

申请日：2022-04-11

Applicant: INTEL CORPORATION

Inventor： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

公开(公告)号：US20240054039A1

公开(公告)日：2024-02-15

申请号：US18258298

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vasudevan SRINIVASAN ,  Knut GRIMSRUD ,  Johan VAN DE GROENENDAAL ,  Mariusz ORIOL ,  Nishi AHUJA ,  Shen ZHOU ,  Samantha ALT ,  Katalin BARTFAI-WALCOTT ,  Arkadiusz BERENT

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0721 ,  G06F11/076

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature configuration pay-as-you-go licensing are disclosed. A disclosed silicon semiconductor device includes a first counter that increments a first count when a timer expires and, responsive to expiration of the timer, a feature configuration sampler to sample a state of a configuration of a feature of the silicon semiconductor device. In addition, the silicon semiconductor device includes a second counter that increments a second count when the sampled state of the configuration of the feature indicates the feature is active. A feature up-time tracker is also included outputs a value representative of an amount of time the configuration has been active, where the amount of time is based on the first count and the second count.

公开(公告)号：US20200225724A1

公开(公告)日：2020-07-16

申请号：US16833008

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Chris MACNAMARA ,  John J. BROWNE ,  Tomasz KANTECKI ,  David HUNT ,  Anatoly BURAKOV ,  Srihari MAKINENI ,  Nikhil GUPTA ,  Ankush VARMA ,  Dorit SHAPIRA ,  Vasudevan SRINIVASAN ,  Bryan T. BUTTERS ,  Shrikant M. SHAH

IPC: G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F1/20

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

公开(公告)号：US20190384348A1

公开(公告)日：2019-12-19

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan SRINIVASAN ,  Krishnakanth V. SISTLA ,  Corey D. GOUGH ,  Ian M. STEINER ,  Nikhil GUPTA ,  Vivek GARG ,  Ankush VARMA ,  Sujal A. VORA ,  David P. LERNER ,  Joseph M. SULLIVAN ,  Nagasubramanian GURUMOORTHY ,  William J. BOWHILL ,  Venkatesh RAMAMURTHY ,  Chris MACNAMARA ,  John J. BROWNE ,  Ripan DAS

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20170160707A1

公开(公告)日：2017-06-08

申请号：US14958424

申请日：2015-12-03

Applicant: INTEL CORPORATION

Inventor： Vasudevan SRINIVASAN

IPC: G05B15/02 ,  G05D23/19 ,  G05B19/042

CPC classification number: G06F1/3206 ,  G06F1/203 ,  G06F1/206

Abstract: An electronic device may perform thermal management operations. The electronic device may receive thermal rating information, and determine an adjusted thermal threshold based on a previous temperature threshold and the thermal rating information. The electronic device may further store the adjusted thermal threshold, and control performance of the electronic device based on the adjusted thermal threshold.