公开(公告)号：US20240421025A1

公开(公告)日：2024-12-19

申请号：US18290289

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Lianchang DU ,  Jeffory L. SMALLEY ,  Srikant NEKKANTY ,  Eric W. BUDDRIUS ,  Yi ZENG ,  Xinjun ZHANG ,  Maoxin YIN ,  Zhichao ZHANG ,  Chen ZHANG ,  Yuehong FAN ,  Mingli ZHOU ,  Guoliang YING ,  Yinglei REN ,  Chong J. ZHAO ,  Jun LU ,  Kai WANG ,  Timothy Glen HANNA ,  Vijaya K. BODDU ,  Mark A. SCHMISSEUR ,  Lijuan FENG

IPC: H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01R13/627

Abstract: A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.

公开(公告)号：US20240281150A1

公开(公告)日：2024-08-22

申请号：US18650966

申请日：2024-04-30

Applicant: Intel Corporation

Inventor： Yi ZENG ,  Kaushik BALASUBRAMANIAN ,  Eti BAYEVSKY ,  Yuli BARCOHEN ,  Lukasz GOLAWSKI ,  Yaniv NISSIM

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Examples described herein relate to an interface to a serial connection and circuitry to: prior to issuance of a read request to a device, issue a command to the device to identify data to be requested to be read and based on an indicator that the identified data is available to be read, send the read request for the identified data via the interface to the device. The command can include an operational code, a starting address, and length.

公开(公告)号：US20240303343A1

公开(公告)日：2024-09-12

申请号：US18666693

申请日：2024-05-16

Applicant: Intel Corporation

Inventor： Yi ZENG ,  Russell J. WUNDERLICH ,  Janusz JURSKI ,  Lumin ZHANG ,  Kasper WSZOLEK ,  Jeanne GUILLORY ,  Ching Yu LO ,  Teresa C. HERRICK ,  Richard Marian THOMAIYAR

IPC: G06F21/57 ,  G06F1/06

CPC classification number: G06F21/575 ,  G06F1/06 ,  G06F21/572

Abstract: Examples described herein relate to multiple processor sockets comprising processors connected thereto and first circuitry. The first circuitry is to: based on a first mode of operation: configure the multiple processor sockets to operate with a single memory address space and share interfaces and based on a second mode of operation: configure the interfaces accessible to the multiple processor sockets to provide isolated communications to processor sockets in different partitions and configure the multiple processor sockets to operate in independent memory address spaces.

公开(公告)号：US20220109733A1

公开(公告)日：2022-04-07

申请号：US17550883

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Kefei ZHANG ,  Fusheng ZHAO ,  Yi ZENG ,  Shihwei CHIEN

IPC: H04L67/51

Abstract: Examples described herein relate to a system for offloading microservice-to-microservice communication to a network interface device.

公开(公告)号：US20240281375A1

公开(公告)日：2024-08-22

申请号：US18651039

申请日：2024-04-30

Applicant: Intel Corporation

Inventor： Ramamurthy KRITHIVAS ,  Yi ZENG ,  Rahul SHAH ,  Krzysztof WOJCIK

IPC: G06F12/08

CPC classification number: G06F12/08 ,  G06F2212/16

Abstract: Examples described herein relate to communications with a bootable processor. Some examples include allocating memory address space to provide access to communications over general purpose input output (GPIO)-consistent pins, wherein the GPIO-consistent pins comprise pins coupled to the bootable processor and a pin of the pins coupled to the bootable processor receives or transmits communication for multiple platform GPIO pins.

公开(公告)号：US20240289202A1

公开(公告)日：2024-08-29

申请号：US18656375

申请日：2024-05-06

Applicant: Intel Corporation

Inventor： Divya GUPTA ,  Raed AL-OMARI ,  Yi ZENG ,  Sheng HUANG

IPC: G06F11/07 ,  G06F9/4401 ,  G06F13/42

CPC classification number: G06F11/0787 ,  G06F9/4401 ,  G06F13/4282 ,  G06F2213/0002

Abstract: Examples described herein relate to a bootable processor that comprises circuitry to load boot firmware. The bootable processor can execute a firmware that is to collect an error log of an error during boot of the bootable processor and that occurred prior to enablement of an Out of Band (OOB) manageability port. The firmware can cause output of the error log to a second circuitry through an interface that is operational prior to enablement of the OOB manageability port.