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    Deep trench capacitor for SOI CMOS devices for soft error immunity
    1.
    发明授权
    Deep trench capacitor for SOI CMOS devices for soft error immunity 有权
    用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度

    公开(公告)号：US07989865B2

    公开(公告)日：2011-08-02

    申请号：US12200538

    申请日：2008-08-28

    申请人： John Edward Barth, Jr. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

    发明人： John Edward Barth, Jr. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

    摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

    摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

    DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY
    2.
    发明申请
    DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY 有权
    用于软错误免疫的SOI CMOS器件的深度TRENCH电容器

    公开(公告)号：US20100052026A1

    公开(公告)日：2010-03-04

    申请号：US12200538

    申请日：2008-08-28

    申请人： John Edward Barth, JR. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

    发明人： John Edward Barth, JR. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

    摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

    摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

    MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS
    5.
    发明申请
    MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS 审中-公开
    监测硅绝缘子集成电路中的离子化辐射

    公开(公告)号：US20090113357A1

    公开(公告)日：2009-04-30

    申请号：US11923784

    申请日：2007-10-25

    申请人： Wagdi William Abadeer ,  Ethan Harrison Cannon ,  Dennis Thomas Cox ,  William Robert Tonti

    发明人： Wagdi William Abadeer ,  Ethan Harrison Cannon ,  Dennis Thomas Cox ,  William Robert Tonti

    IPC分类号： G06F17/50

    CPC分类号： H01L31/103 ,  G11C5/005 ,  G11C11/4125 ,  H01L31/115 ,  H01L31/118 ,  H03K19/0033

    摘要： A method, device and system for monitoring ionizing radiation, and design structures for ionizing radiation monitoring devices. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.

    摘要翻译： 用于监测电离辐射的方法，装置和系统，以及用于电离辐射监测装置的设计结构。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。

    Method for neutralizing trapped charge in a charge accumulation layer of a semiconductor structure
    6.
    发明授权
    Method for neutralizing trapped charge in a charge accumulation layer of a semiconductor structure 失效
    用于中和半导体结构的电荷累积层中的俘获电荷的方法

    公开(公告)号：US07736915B2

    公开(公告)日：2010-06-15

    申请号：US11276248

    申请日：2006-02-21

    申请人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

    发明人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

    IPC分类号： H01L21/00 ,  H01L31/00 ,  H01L31/0248 ,  H01L31/0352

    CPC分类号： H01L21/743 ,  H01L21/76275

    摘要： A method for neutralizing trapped charges in a buried oxide layer. The method includes providing a semiconductor structure which includes (a) a semiconductor layer, (b) a charge accumulation layer on top of the semiconductor layer, and (c) a doped region in direct physical contact with the semiconductor layer, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode. Next, free charges are generated in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign. Next, the free charges are accelerated towards the charge accumulation layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.

    摘要翻译： 一种用于中和掩埋氧化物层中的俘获电荷的方法。 该方法包括提供半导体结构，该半导体结构包括（a）半导体层，（b）半导体层顶部的电荷累积层，和（c）与该半导体层直接物理接触的掺杂区域，其中电荷累积 层包括第一符号的俘获电荷，并且其中所述掺杂区域和所述半导体层形成PN结二极管。 接下来，在P-N结二极管中产生自由电荷，其中自由电荷是与第一符号相反的第二符号。 接下来，免费电荷朝向电荷累积层加速，导致一些自由电荷进入电荷累积层并中和电荷累积层中的一些俘获电荷。

    Shallow trench isolation method for shielding trapped charge in a semiconductor device
    8.
    发明授权
    Shallow trench isolation method for shielding trapped charge in a semiconductor device 失效
    用于屏蔽半导体器件中的俘获电荷的浅沟槽隔离方法

    公开(公告)号：US07385275B2

    公开(公告)日：2008-06-10

    申请号：US11276132

    申请日：2006-02-15

    申请人： Ethan Harrison Cannon ,  Shunhua Thomas Chang ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III

    发明人： Ethan Harrison Cannon ,  Shunhua Thomas Chang ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III

    IPC分类号： H01L29/00 ,  H01L21/762 ,  H01L21/763

    CPC分类号： H01L21/76224 ,  H01L29/7833

    摘要： A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.

    摘要翻译： 一种用于形成半导体结构的半导体结构和相关方法。 半导体结构包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构。 第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。 沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。 导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

    NEUTRALIZATION OF TRAPPED CHARGE IN A CHARGE ACCUMULATION LAYER OF A SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    NEUTRALIZATION OF TRAPPED CHARGE IN A CHARGE ACCUMULATION LAYER OF A SEMICONDUCTOR STRUCTURE 有权
    半导体结构电荷积累层中俘获电荷的中和

    公开(公告)号：US20100237475A1

    公开(公告)日：2010-09-23

    申请号：US12792837

    申请日：2010-06-03

    申请人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

    发明人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

    IPC分类号： H01L29/06

    CPC分类号： H01L21/743 ,  H01L21/76275

    摘要： A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P-N junction diode. The P-N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.

    摘要翻译： 半导体结构。 半导体结构包括半导体层，在半导体层顶部的电荷累积层，与半导体层直接物理接触的掺杂区域; 以及与电荷累积层直接物理接触的器件层。 电荷累积层包括第一符号的俘获电荷。 掺杂区域和半导体层形成P-N结二极管。 P-N结二极管包括与第一个符号相反的第二个符号的免费电荷。 电荷累积层中的俘获电荷超过预设极限，超过该限制，半导体结构被配置为故障。 第一电压被施加到掺杂区域。 向半导体层施加第二电压。 第三电压被施加到器件层。 第三电压超过第一电压和第二电压。