SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20240074172A1

    公开(公告)日:2024-02-29

    申请号:US18181821

    申请日:2023-03-10

    CPC classification number: H10B41/27 H10B43/27

    Abstract: In one embodiment, a semiconductor storage device includes a lower electrode layer, a lower insulator, an upper electrode layer and an upper insulator along a first direction. The device further includes a first insulator provided on a side of a second direction of the upper electrode layer, and a second insulator provided between the upper electrode layer and the lower/upper/first insulator. The device further includes a charge storage layer, a third insulator and a semiconductor layer sequentially provided on a side of the second direction of the first insulator. A side face of the first insulator on a side of the upper electrode layer has a convex shape, the charge storage layer includes a first portion having a first thickness, and a second portion having a second thickness less than the first thickness, and the first portion is in contact with the first insulator.

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

    公开(公告)号:US20230048781A1

    公开(公告)日:2023-02-16

    申请号:US17695280

    申请日:2022-03-15

    Abstract: A method for manufacturing a semiconductor device of an embodiment includes: forming a first film on a semiconductor layer containing silicon (Si), the first film containing a metal element and oxygen (O) and having a first thickness; and forming a second film between the semiconductor layer and the first film using radical oxidation, the second film containing silicon (Si) and oxygen (O) and having a second thickness larger than the first thickness.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20240324227A1

    公开(公告)日:2024-09-26

    申请号:US18593379

    申请日:2024-03-01

    CPC classification number: H10B43/35 H10B43/27

    Abstract: A semiconductor device includes a stack including a conductor layer and an insulator layer, a block insulating layer, a channel layer, a charge storage layer provided between the block insulating layer and the channel layer, and a tunnel layer provided between the charge storage layer and the channel layer, where the charge storage layer includes a first charge storage layer containing Si, N and at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P, a second charge storage layer containing Si and N, in which Si is contained at a second concentration higher than a first concentration that is a concentration of Si in the first charge storage layer, and provided between the first charge storage layer and the tunnel layer, and a dielectric layer containing at least one of silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or aluminum oxide (AlOx), and provided between the first charge storage layer and the second charge storage layer.

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