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    MEMORY SYSTEM AND METHOD
    1.
    发明公开
    MEMORY SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20240201866A1

    公开(公告)日：2024-06-20

    申请号：US18461659

    申请日：2023-09-06

    Applicant: Kioxia Corporation

    Inventor： Atsuo SHONO ,  Kiyotaka IWASAKI

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/023

    Abstract: According to an embodiment, a memory system includes a memory controller. At a first timing within a period from allocation of an area unit to completion of a data-in operation on the data unit stored in an area unit, the memory controller deallocates the area unit upon the completion of the data-in operation on the data unit when a usage of a buffer area is smaller than a first threshold value. At the first timing, the memory controller deallocates the area unit upon completion of the program operation on the data unit when the usage of the buffer area is larger than a second threshold value. The second threshold value is larger than the first threshold value.

    NONVOLATILE MEMORY INCLUDING INTERMEDIATE BUFFER AND INPUT/OUTPUT BUFFER AND MEMORY SYSTEM INCLUDING THE NONVOLATILE MEMORY
    3.
    发明申请
    NONVOLATILE MEMORY INCLUDING INTERMEDIATE BUFFER AND INPUT/OUTPUT BUFFER AND MEMORY SYSTEM INCLUDING THE NONVOLATILE MEMORY 有权

    公开(公告)号：US20230056583A1

    公开(公告)日：2023-02-23

    申请号：US17982840

    申请日：2022-11-08

    Applicant: Kioxia Corporation

    Inventor： Yoshihisa KOJIMA ,  Masanobu SHIRAKAWA ,  Kiyotaka IWASAKI

    IPC: G06F3/06

    Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.

    MEMORY SYSTEM
    5.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240094947A1

    公开(公告)日：2024-03-21

    申请号：US18337137

    申请日：2023-06-19

    Applicant: Kioxia Corporation

    Inventor： Atsuo SHONO ,  Kiyotaka IWASAKI

    IPC: G06F3/06

    CPC classification number: G06F3/0658 ,  G06F3/0679 ,  G06F3/0604

    Abstract: According to one embodiment, a system includes: a memory, and a controller, wherein the memory includes a first die including first and second planes and a second die including a third plane, and the controller issues a read command to the first and second dies, if a read time for first data in the first plane has ended, a read time for second data in the second plane has ended after the end of the read time for the first data, and a read time for third data in the third plane has ended after the end of the read time for the second data, receives the first data from the first die, receives the third data from the second die after completion of receiving the first data, and receives the second data from the first die after completion of receiving the third data.

    MEMORY SYSTEM
    8.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240094940A1

    公开(公告)日：2024-03-21

    申请号：US18460284

    申请日：2023-09-01

    Applicant: Kioxia Corporation

    Inventor： Kensaku YAMAGUCHI ,  Kiyotaka IWASAKI ,  Takashi TAKEMOTO ,  Kohei OIKAWA

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0608 ,  G06F3/0679

    Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform a write operation of a first data cluster and a first partial overwrite operation of the first data cluster with first overwrite data. The write operation includes compressing and then encrypting the first data cluster, and writing the compressed and encrypted first data cluster into a first physical location of the non-volatile memory. The first partial overwrite operation includes encrypting the first overwrite data without performing compression, reading the compressed and encrypted first data cluster from the first physical location of the non-volatile memory, generating a first composite data cluster with the compressed and encrypted first data cluster read from the first physical location and the encrypted first overwrite data that is not compressed, and writing the first composite data cluster into a second physical location of the non-volatile memory.

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