公开(公告)号：US20220302166A1

公开(公告)日：2022-09-22

申请号：US17744571

申请日：2022-05-13

Applicant: Kioxia Corporation

Inventor： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Akihiro NITAYAMA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yoshiaki FUKUZUMI ,  Yasuyuki MATSUOKA ,  Mitsuru SATO

IPC: H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US20220157784A1

公开(公告)日：2022-05-19

申请号：US17590373

申请日：2022-02-01

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20240038731A1

公开(公告)日：2024-02-01

申请号：US18486194

申请日：2023-10-13

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L24/08 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L2224/05025 ,  H01L24/05 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2224/08146 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/0401

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20230345726A1

公开(公告)日：2023-10-26

申请号：US18339526

申请日：2023-06-22

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi TAGAMI ,  Jun IIJIMA ,  Ryota KATSUMATA ,  Kazuyuki HIGASHI

IPC: H10B43/27 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L25/0657 ,  H01L24/04 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20210126011A1

公开(公告)日：2021-04-29

申请号：US17141504

申请日：2021-01-05

Applicant: Kioxia Corporation

Inventor： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Akihiro NITAYAMA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yoshiaki FUKUZUMI ,  Yasuyuki MATSUOKA ,  Mitsuru SATO

IPC: H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US20220328517A1

公开(公告)日：2022-10-13

申请号：US17750207

申请日：2022-05-20

Applicant: Kioxia Corporation

Inventor： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Akihiro NITAYAMA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yoshiaki FUKUZUMI ,  Yasuyuki MATSUOKA ,  Mitsuru SATO

IPC: H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US20220320138A1

公开(公告)日：2022-10-06

申请号：US17843320

申请日：2022-06-17

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/105 ,  H01L29/51

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20220246631A1

公开(公告)日：2022-08-04

申请号：US17726081

申请日：2022-04-21

Applicant: KIOXIA CORPORATION

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H01L27/11556 ,  H01L21/768 ,  H01L21/74 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11578 ,  H01L23/535 ,  H01L27/11573 ,  H01L25/00

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20220028892A1

公开(公告)日：2022-01-27

申请号：US17499357

申请日：2021-10-12

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H01L27/11582 ,  H01L27/11573

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20240397722A1

公开(公告)日：2024-11-28

申请号：US18798312

申请日：2024-08-08

Applicant: Kioxia Corporation

Inventor： Masayoshi TAGAMI ,  Jun IIJIMA ,  Ryota KATSUMATA ,  Kazuyuki HIGASHI

IPC: H10B43/27 ,  G11C5/02 ,  G11C16/04 ,  G11C16/26 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.