公开(公告)号：US20230411327A1

公开(公告)日：2023-12-21

申请号：US18176474

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Masayoshi TAGAMI

IPC: H01L23/00 ,  H10B80/00 ,  H01L25/16

CPC classification number: H01L24/08 ,  H10B80/00 ,  H01L24/09 ,  H01L24/05 ,  H01L25/16 ,  H01L2224/05005 ,  H01L2224/05014 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05573 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/0903 ,  H01L2224/09051 ,  H01L2224/0801 ,  H01L2224/08055 ,  H01L2224/08057 ,  H01L2224/08145 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2224/05647 ,  H01L2224/05554

Abstract: According to one embodiment, a semiconductor device includes a first chip with a first electrode and a second electrode and a second chip with a third electrode and a fourth electrode. The first and second chips are bonded to each other with the first electrode contacting the third electrode and the second electrode contacting the fourth electrode. A thickness of the first electrode in a first direction perpendicular to a bonding interface between the first chip and the second chip is less than a thickness of the second electrode in the first direction. A planar area of the first electrode at the bonding interface is greater than a planar area of the second electrode at the bonding interface.

公开(公告)号：US20220157784A1

公开(公告)日：2022-05-19

申请号：US17590373

申请日：2022-02-01

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20210265293A1

公开(公告)日：2021-08-26

申请号：US17009234

申请日：2020-09-01

Applicant: Kioxia Corporation

Inventor： Masayoshi TAGAMI

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a substrate, a first interconnection provided above the substrate, and a first pad provided on the first interconnection. The device further includes a second pad provided on the first pad, and a second interconnection provided on the second pad. Furthermore, the first pad includes a first layer provided in a first insulator above the substrate, and a second layer that is provided in the first insulator via the first layer and is in contact with the first interconnection, or the second pad includes a third layer provided in a second insulator above the substrate, and a fourth layer that is provided in the second insulator via the third layer and is in contact with the second interconnection.

公开(公告)号：US20250132276A1

公开(公告)日：2025-04-24

申请号：US19007801

申请日：2025-01-02

Applicant: Kioxia Corporation

Inventor： Masayoshi TAGAMI

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/18 ,  H10B43/27

Abstract: In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

公开(公告)号：US20250070023A1

公开(公告)日：2025-02-27

申请号：US18808257

申请日：2024-08-19

Applicant: Kioxia Corporation

Inventor： Hisashi KATO ,  Masayoshi TAGAMI ,  Akira NAKAJIMA

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a first chip including a first insulating layer; a second chip bonded to the first chip and including a second insulating layer; and a pad provided around a bonded surface between the first chip and the second chip. The pad includes a first metal layer including a first metal, a second metal layer disposed between the first metal layer and the first insulating layer, and a third metal layer disposed between the first metal layer and the second insulating layer. At least one of the second metal layer or the third metal layer include a second metal having oxidation energy lower than oxidation energy of the first metal. The first metal layer further includes the second metal.

公开(公告)号：US20230395497A1

公开(公告)日：2023-12-07

申请号：US18176431

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Hiroyuki YAMASAKI ,  Masayoshi TAGAMI

IPC: H01L23/528 ,  H01L23/522 ,  H10B80/00 ,  H01L25/18 ,  H10B41/20 ,  H10B43/20 ,  H10B41/10 ,  H10B43/10

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B80/00 ,  H10B43/10 ,  H10B41/20 ,  H10B43/20 ,  H10B41/10 ,  H01L25/18

Abstract: According to one embodiment, a semiconductor storage device includes a first chip, a second chip, and a third chip. In the third chip, a first conductive film is above a first stacked body. The first conductive film extends across the first stacked body when viewed from a stacking direction. A first plug extends in the stacking direction and connects the first conductive film and a second conductive film. The first electrode is connected to the second conductive film. In the second chip, a third conductive film is above a second stacked body. A second plug extends in the stacking direction and connects the third conductive film and the fourth conductive film. The second electrode is connected to the fourth conductive film. The first chip has a first wiring structure therein. The first wiring structure is connected to the second electrode.

公开(公告)号：US20250029956A1

公开(公告)日：2025-01-23

申请号：US18777303

申请日：2024-07-18

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Hisashi KATO ,  Hiroaki ASHIDATE ,  Masayoshi TAGAMI

IPC: H01L25/065 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device includes first and second chips that are bonded together. The first chip includes a stacked body in which memory cells are formed and first bonding electrodes, and the second chip includes second bonding electrodes. The first bonding electrodes and the second bonding electrodes are joined to each other to form joining electrodes. The stacked body includes an insulating layer that extends in a first direction to separate the stacked body in a second direction. The joining electrodes include first and second joining electrodes, the first joining electrodes being disposed adjacent to a first side of the insulating layer in a third direction, and the second joining electrodes being disposed adjacent to a second side of the insulating layer in the third direction. The first joining electrodes and the second joining electrodes are disposed in a staggered arrangement in the second direction and the third direction.

公开(公告)号：US20240292619A1

公开(公告)日：2024-08-29

申请号：US18586775

申请日：2024-02-26

Applicant: Kioxia Corporation

Inventor： Yasuaki NAKATA ,  Masayoshi TAGAMI ,  Koichi SAKATA ,  Miki TOSHIMA

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes transistors disposed on a substrate; a first metal wiring layer disposed over the transistors at a first position, the first metal wiring layer including a first metal wiring; a stacked body, disposed above the first metal wiring layer, including a first conductive layers and first insulating layers alternately stacked; a pillar including a semiconductor layer that includes a first type impurity in an upper end and penetrates through the stacked body; and a second conductive layer disposed at a second position further from the substrate than the first position, overlapped with the first metal wiring or another metal wiring in the first metal wiring layer, and not electrically connected to any of the transistors, the first conductive layers, or the first metal wiring layer. The second conductive layer has a higher melting point than the first metal wiring.

公开(公告)号：US20220406743A1

公开(公告)日：2022-12-22

申请号：US17894219

申请日：2022-08-24

Applicant: Kioxia Corporation

Inventor： Masayoshi TAGAMI

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/18 ,  H01L27/11582

Abstract: In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

公开(公告)号：US20220189905A1

公开(公告)日：2022-06-16

申请号：US17350473

申请日：2021-06-17

Applicant: Kioxia Corporation

Inventor： Genki SAWADA ,  Masayoshi TAGAMI ,  Jun IIJIMA ,  Ippei KUME ,  Kiyomitsu YOSHIDA

IPC: H01L23/00 ,  H01L25/18

Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.