公开(公告)号：US20240086077A1

公开(公告)日：2024-03-14

申请号：US18181824

申请日：2023-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

公开(公告)号：US20220223552A1

公开(公告)日：2022-07-14

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: H01L23/00 ,  H01L23/544 ,  G06F11/07

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US20220066921A1

公开(公告)日：2022-03-03

申请号：US17184313

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Daisuke IWAI ,  Toshio FUJISAWA ,  Keigo HARA

IPC: G06F12/02 ,  G06F12/06

Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

公开(公告)号：US20220083261A1

公开(公告)日：2022-03-17

申请号：US17335511

申请日：2021-06-01

Applicant: Kioxia Corporation

Inventor： Daisuke FUJIWARA ,  Tomoya SANUKI ,  Toshio FUJISAWA

IPC: G06F3/06

Abstract: A memory system of an embodiment includes a NAND memory and a memory controller. The NAND memory includes an encoder configured to convert first data into second data including a plurality of code words generated by dividing the first data into the code words, generate parity data in a horizontal direction of the second data for error check and correct for each code word and encode the first data, and a decoder. A control circuit of the NAND memory controls the decoder to perform hard decision decoding using the parity data in the horizontal direction on readout target data when a readout command is received and outputs the decoded readout target data to the memory controller when the hard decision decoding of the readout target data is successful.

公开(公告)号：US20220011963A1

公开(公告)日：2022-01-13

申请号：US17197667

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Yuta AIBA ,  Hitomi TANAKA ,  Masayuki MIURA ,  Mie MATSUO ,  Toshio FUJISAWA ,  Takashi MAEDA

IPC: G06F3/06

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of −40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of −40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

公开(公告)号：US20240070062A1

公开(公告)日：2024-02-29

申请号：US18502498

申请日：2023-11-06

Applicant: Kioxia Corporation

Inventor： Daisuke IWAI ,  Toshio FUJISAWA ,  Keigo HARA

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F2212/202 ,  G06F2212/403 ,  G06F2212/7205

Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

公开(公告)号：US20230017909A1

公开(公告)日：2023-01-19

申请号：US17681547

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Daisuke FUJIWARA ,  Toshio FUJISAWA

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097

Abstract: A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

公开(公告)号：US20220301599A1

公开(公告)日：2022-09-22

申请号：US17475482

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Xu LI ,  Masayuki MIURA ,  Takayuki MIYAZAKI ,  Toshio FUJISAWA ,  Hiroto NAKAI ,  Hideko MUKAIDA ,  Mie MATSUO

IPC: G11C5/14 ,  H01L27/11556 ,  H01L27/11582 ,  H02M3/158 ,  G11C16/30

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

公开(公告)号：US20220320065A1

公开(公告)日：2022-10-06

申请号：US17847528

申请日：2022-06-23

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Toshio FUJISAWA ,  Hiroshi MAEJIMA ,  Takashi MAEDA

IPC: H01L25/18 ,  H01L23/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F3/06

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

公开(公告)号：US20220204270A1

公开(公告)日：2022-06-30

申请号：US17694532

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: B65G1/137

Abstract: According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.