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公开(公告)号：US5640355A
公开(公告)日：1997-06-17
申请号：US471507
申请日：1995-06-06
IPC分类号： G11C11/419 , G11C7/06 , G11C7/12 , G11C11/401 , G11C11/409 , G11C7/00
摘要： A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.
摘要翻译： 一种包括存储单元阵列，位线和读出放大器组的半导体存储器件。 存储单元阵列由大致矩阵排列的多个存储单元构成。 响应于行地址解码信号，激活了排成行的多个存储单元。 为每列提供一对位线。 相应的激活的存储器单元的数据被发送到位线对。 读出放大器组中的每一个具有各自连接到位线对的读出放大器的n个单元，以检测和放大读取到与其连接的位线对的数据。 每个读出放大器组的读出放大器的相应参考电位端子连接到单个公共节点，该公共节点可以响应于行地址信号经由读出放大器激活晶体管导通而连接到参考电位。 由于读出放大器的公共源节点的布线电阻和寄生电容可以减小，所以读出放大器可以高速操作，同时防止错误的操作。
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公开(公告)号：US5848011A
公开(公告)日：1998-12-08
申请号：US824737
申请日：1997-03-26
IPC分类号： G11C11/419 , G11C7/06 , G11C7/12 , G11C11/401 , G11C11/409 , G11C7/00
摘要： A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.
摘要翻译： 一种包括存储单元阵列，位线和读出放大器组的半导体存储器件。 存储单元阵列由大致矩阵排列的多个存储单元构成。 响应于行地址解码信号，激活了排成行的多个存储单元。 为每列提供一对位线。 相应的激活的存储器单元的数据被发送到位线对。 读出放大器组中的每一个具有各自连接到位线对的读出放大器的n个单元，以检测和放大读取到与其连接的位线对的数据。 每个读出放大器组的读出放大器的各个参考电位端子连接到单个公共节点，该公共节点可以响应于行地址信号经由读出放大器激活晶体管导通而连接到参考电位。 由于读出放大器的公共源节点的布线电阻和寄生电容可以减小，所以读出放大器可以高速操作，同时防止错误的操作。
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3.发明授权Semiconductor memory having a plurality of sense amplifier circuits and corresponding bit lines 失效半导体存储器具有多个读出放大器电路和对应的位线
公开(公告)号：US5270971A
公开(公告)日：1993-12-14
申请号：US677442
申请日：1991-03-29
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C7/00
CPC分类号： G11C7/065
摘要： An improved semiconductor memory having a plurality of sense amplifier circuits corresponding to each bit line of a plurality of columns. A first common line is connected in common to the sense amplifier circuits, and a second common line is connected to the first common line. A first switching element is connected between the second common line and a reference voltage potential terminal, and a second switching element is connected to the first common line and the reference voltage potential. The second switching element corresponding to the first common line connected to one of the sense amplifier circuits is made conductive in response to a selection of the sense amplifier is disclosed.
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公开(公告)号：US5570047A
公开(公告)日：1996-10-29
申请号：US298837
申请日：1994-08-31
IPC分类号： G11C11/409 , G11C5/14 , H03K5/153 , G11C7/00
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit includes memory cell blocks having memory cells arranged in matrix, sense amplifiers, each located adjacent to the memory cells, and sense amplifier control circuits, each of the sense amplifier control circuit being located on outside of the memory cell block. The sense amplifier control circuit has a standard voltage generating circuit and a control circuit for receiving the standard voltage and for transferring a driver signal to the sense amplifier to control the charging ability of the sense amplifier. The source voltage has three voltage regions, first, intermediate, and second regions. In the first voltage region, the potential of the driver signal increases with the increase of the source voltage. In the intermediate voltage region (2.7 to 3 Volt), the potential of the driver signal is changed oppose to the change of the source voltage, and in the second voltage region, the potential of the driver signal decreases with the increase of the source voltage.
摘要翻译： 半导体集成电路包括具有排列成矩阵的存储单元的存储单元块，每个位于与存储单元相邻的读出放大器，以及读出放大器控制电路，每个读出放大器控制电路位于存储单元块的外部。 读出放大器控制电路具有标准电压发生电路和用于接收标准电压并将驱动器信号传送到读出放大器以控制读出放大器的充电能力的控制电路。 源电压具有三个电压区域，第一，中间和第二区域。 在第一电压区域中，驱动信号的电位随源电压的增加而增加。 在中间电压区域（2.7〜3伏特）中，驱动信号的电位相对于源极电压的变化而变化，在第二电压区域中，驱动信号的电位随着源极电压的增加而减小 。
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公开(公告)号：US5391918A
公开(公告)日：1995-02-21
申请号：US80512
申请日：1993-06-24
CPC分类号： H01L23/50 , H01L23/4951 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/181
摘要： In the semiconductor device according to the present invention, bonding pads are arranged on the periphery of the semiconductor chip and power supply inner leads are disposed inwardly of signal inner leads. Since bonding wires for connecting the signal lead to signal pads corresponding thereto do not extend astride of the power supply inner lead, a package of a semiconductor device can be thereby thinned as much as possible.
摘要翻译： 在本发明的半导体装置中，在半导体芯片的周边配置接合焊盘，电源内引线配置在信号内引线的内侧。 由于用于将信号引线连接到与其相对应的信号焊盘的接合线不跨越电源内引线延伸，所以可以尽可能地减薄半导体器件的封装。
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公开(公告)号：US5168462A
公开(公告)日：1992-12-01
申请号：US585703
申请日：1990-09-20
申请人： Yoshiaki Takeuchi , Masaru Koyanagi
发明人： Yoshiaki Takeuchi , Masaru Koyanagi
IPC分类号： G11C11/401 , G11C5/06 , G11C7/06 , G11C7/18 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： In a semiconductor memory device having plural pairs of bit lines and plural sense amplifiers, a gate electrode of a sense amplifier transistor for sensing potential of a first side of a first bit line pair is formed with an extension portion extending under and along the first side of a second bit line pair. A capacitance C.sub.B formed between the extension of the gate electrode and the first side of the second bit line pair is determined to be equal or larger than capacitance C.sub.A formed between the first side of the first bit line pair and the gate electrode. Since the potential of the first side of the bit line pair fluctuates roughly in phase with that of the second side of the same bit line pair, a harmful influence due to interference noise can be reduced, without increasing the chip layout area, by only modifying the shapes of the gate electrodes of the sense amplifier transistors.
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公开(公告)号：US5627493A
公开(公告)日：1997-05-06
申请号：US519249
申请日：1995-08-25
IPC分类号： G05F1/56 , G05F1/46 , G11C5/00 , G11C5/14 , G11C11/407 , G11C11/408 , G11C11/413 , H03K19/00 , G05F3/02
摘要： The semiconductor device comprises: an internal supply voltage deboosting circuit for inputting an external supply voltage, deboosting the inputted external supply voltage, and outputting a deboosted voltage as an internal supply voltage; a first control circuit for deactivating the internal supply voltage deboosting circuit when the external supply voltage is lower than a predetermined value; and a second control circuit for outputting the external supply voltage as the internal supply voltage when the external supply voltage is lower than the predetermined value. When the external supply voltage is lower than a predetermined value, since the internal supply voltage deboosting circuit is deactivated by the first control circuit, the current consumption can be reduced. Further, since the external supply voltage is outputted as the internal supply voltage by the second control circuit, the deboosting operation is not required. The device is usable for different external supply voltages in spite of the same circuit configuration, while preventing the operational margin from being deteriorated.
摘要翻译： 半导体器件包括：用于输入外部电源电压的内部电源电压去抖动电路，去除所输入的外部电源电压，并输出去激发的电压作为内部电源电压; 第一控制电路，用于当所述外部电源电压低于预定值时停止所述内部电源电压去抖动电路; 以及第二控制电路，用于当外部电源电压低于预定值时输出外部电源电压作为内部电源电压。 当外部电源电压低于预定值时，由于内部电源电压去保护电路被第一控制电路停用，所以可以减少电流消耗。 此外，由于通过第二控制电路输出外部电源电压作为内部电源电压，因此不需要去抖动操作。 尽管有相同的电路配置，该器件可用于不同的外部电源电压，同时防止操作裕度恶化。
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公开(公告)号：US08736346B2
公开(公告)日：2014-05-27
申请号：US13524391
申请日：2012-06-15
申请人： Yuui Shimizu , Masaru Koyanagi
发明人： Yuui Shimizu , Masaru Koyanagi
IPC分类号： H03L5/00
摘要： According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.
摘要翻译： 根据一个实施例，电平移位电路包括彼此连接的多个电平移位单元，其中输出电压的上升沿的延迟时间与输出电压的下降沿的延迟时间不同 。 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元的输出电压的下降沿的延迟时间补偿，并且输出电压的下降沿的延迟时间 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元补偿。
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9.发明授权Output buffer circuit, input buffer circuit, and input/output buffer circuit 有权输出缓冲电路，输入缓冲电路，输入/输出缓冲电路公开(公告)号：US08405432B2
公开(公告)日：2013-03-26
申请号：US12963114
申请日：2010-12-08
IPC分类号： H03K3/01
CPC分类号： H03K19/00384 , H03K19/01721
摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.
摘要翻译： 根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置 以使得能够选择性地驱动多个缓冲电路。 多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据 控制信号由外部提供。 包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。
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公开(公告)号：US20110128063A1
公开(公告)日：2011-06-02
申请号：US12884533
申请日：2010-09-17
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.
摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二电平移位电路。 第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。 第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号 移位器被输入。 第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。
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